公开(公告)号：US06482726B1

公开(公告)日：2002-11-19

申请号：US09690152

申请日：2000-10-17

Applicant: Massud Aminpur ,  David Wu ,  Scott Luning

Inventor： Massud Aminpur ,  David Wu ,  Scott Luning

IPC: H01L213205

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.

Abstract translation: 提供了一种方法，该方法包括在衬底层上方形成栅介质层，在栅极介电层上方形成栅极导体层，在栅极导体层之上形成第一硬掩模层，并形成第二硬掩模层 第一硬掩模层。 该方法还包括在第二硬掩模层之上形成修整的光致抗蚀剂掩模，并且在第二硬掩模层中使用经修剪的光致抗蚀剂掩模形成图案化的硬掩模以去除第二硬掩模层的部分，图案化硬掩模具有第一 尺寸。 该方法还包括通过去除与图案化的硬掩模相邻的第一硬掩模层的部分来形成第一硬掩模层中的选择性蚀刻的硬掩模，该选择性蚀刻的硬掩模具有小于第一尺寸的第二尺寸，以及形成栅极 结构，其使用选择性蚀刻的硬掩模以去除栅极介电层上方的栅极导体层的部分。

公开(公告)号：US06232166B1

公开(公告)日：2001-05-15

申请号：US09187523

申请日：1998-11-06

Applicant: Dong-Hyuk Ju ,  Scott Luning

Inventor： Dong-Hyuk Ju ,  Scott Luning

IPC: H01L218238

CPC classification number: H01L29/66537 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

Abstract: Halo implant regions are formed in a P-channel semiconductor device employing a zero degree tilt angle. N-type impurities are ion implanted to the desired depth in the semiconductor substrate prior to forming P-channel lightly doped source/drain areas. Subsequently, moderately or heavily doped source/drain regions are formed, followed by activation annealing. The halo implants diffuse to form halo structures at the desired location, thereby reducing short channel effects, such as subsurface punchthrough. Other embodiments enable independent control of the junction depths and channel lengths of N- and P-channel transistors, while maintaining high manufacturing throughput.

Abstract translation: 卤素注入区域形成在采用零度倾斜角的P沟道半导体器件中。 在形成P沟道轻掺杂的源极/漏极区之前，将N型杂质离子注入半导体衬底中所需的深度。 随后，形成适度或重掺杂的源极/漏极区，随后进行激活退火。 光晕植入物在期望的位置扩散以形成晕圈结构，从而减少短通道效应，例如地下穿孔。 其他实施例能够独立控制N沟道晶体管和P沟道晶体管的结深度和沟道长度，同时保持高的制造吞吐量。

公开(公告)号：US06180468B2

公开(公告)日：2001-01-30

申请号：US09177774

申请日：1998-10-23

Applicant: Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

Inventor： Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

IPC: H01L21336

CPC classification number: H01L29/66537 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

Abstract: An ultra-low thermal budget process is provided for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally deposited polysilicon gate is removed, a nitride film deposition and etch is used to form a nitride spacer with a predetermined configuration, and a self-aligned channel implant is performed. After the channel implantation, anneal and super-retrograded doping, the nitride spacer and the gate oxide are removed for subsequent regrowth of a second gate oxide and a polysilicon deposition to form a second polysilicon gate.

Abstract translation: 通过使用反向工艺流程为通道注入提供超低热量预算过程，其中形成常规MOS晶体管而不需要沟道注入。 去除原来沉积的多晶硅栅极，使用氮化物膜沉积和蚀刻来形成具有预定配置的氮化物间隔物，并且执行自对准沟道注入。 在通道注入，退火和超退火掺杂之后，去除氮化物间隔物和栅极氧化物，以便随后的第二栅极氧化物的再生长和多晶硅沉积形成第二多晶硅栅极。

公开(公告)号：US6117719A

公开(公告)日：2000-09-12

申请号：US993060

申请日：1997-12-18

Applicant: Scott Luning ,  Emi Ishida

Inventor： Scott Luning ,  Emi Ishida

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L29/66492 ,  H01L21/2255 ,  H01L29/1045 ,  H01L29/6659

Abstract: Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on the side surfaces of the gate electrode. Dopant atoms are subsequently introduce to transform the spacers into solid dopant sources. Dopant atoms are diffused from the spacers into the semiconductor substrate to form first doped regions.

Abstract translation: 通过从栅电极侧壁间隔物的扩散，在半导体衬底的有源区中形成杂质。 在半导体衬底上形成有栅电介质层的栅电极。 侧壁间隔物形成在栅电极的侧表面上。 随后引入掺杂原子以将间隔物转化为固体掺杂剂源。 掺杂原子从间隔物扩散到半导体衬底中以形成第一掺杂区域。

公开(公告)号：US5998272A

公开(公告)日：1999-12-07

申请号：US745475

申请日：1996-11-12

Applicant: Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju

Inventor： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju

IPC: H01L21/223 ,  H01L21/265 ,  H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/223 ,  H01L21/2652 ,  H01L29/665 ,  H01L29/6659

Abstract: A process in accordance with the invention minimizes the number of heat steps to which an source-drain extension region is exposed, thus minimizing source-drain extension region diffusion and allowing more precise control of source-drain extension region thickness over conventional processes. In accordance with the invention, spacers are formed abutting the gate and then heavily doped source and drain regions are formed. The gate and source and drain regions are silicided. The spacers are subsequently removed and source-drain extension regions are then formed. In one embodiment of the invention, a laser doping process is used to form the source-drain extension regions.

Abstract translation: 根据本发明的方法使源极 - 漏极延伸区域暴露的加热步骤的数量最小化，从而使源极 - 漏极延伸区域扩散最小化，并且允许比常规工艺更精确地控制源极 - 漏极扩展区域厚度。 根据本发明，形成邻接栅极的间隔物，然后形成重掺杂的源区和漏区。 栅极和源极和漏极区域被硅化。 随后移除间隔物，然后形成源漏扩展区。 在本发明的一个实施例中，使用激光掺杂工艺来形成源极 - 漏极延伸区域。

公开(公告)号：US5770519A

公开(公告)日：1998-06-23

申请号：US464305

申请日：1995-06-05

Applicant: Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract translation: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属储存器。 储存器由铜的共形层或沉积在通孔上的金形成，以形成位于通孔中的铜或金塞。 在储存器和绝缘层之间设置阻挡层，以防止储存器扩散到绝缘层中。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积阻挡层和储层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和储存器。

公开(公告)号：US08030144B2

公开(公告)日：2011-10-04

申请号：US12576987

申请日：2009-10-09

Applicant: Scott Luning ,  Frank Scott Johnson

Inventor： Scott Luning ,  Frank Scott Johnson

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/336 ,  H01L21/3205

CPC classification number: H01L29/7842 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

Abstract translation: 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

公开(公告)号：US20100308409A1

公开(公告)日：2010-12-09

申请号：US12480263

申请日：2009-06-08

Applicant: Frank S. Johnson ,  Scott Luning ,  Michael J. Hargrove

Inventor： Frank S. Johnson ,  Scott Luning ,  Michael J. Hargrove

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/31 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7843

Abstract: FinFET structures with fins having stress-inducing caps and methods for fabricating such FinFET structures are provided. In an exemplary embodiment, a method for forming stressed structures comprises forming a first stress-inducing material overlying a semiconductor material and forming spacers overlying the first stress-inducing material. The first stress-inducing material is etched using the spacers as an etch mask to form a plurality of first stress-inducing caps. The semiconductor material is etched using the plurality of first stress-inducing caps as an etch mask.

Abstract translation: 提供具有应力诱导帽的翅片的FinFET结构和用于制造这种FinFET结构的方法。 在示例性实施例中，用于形成应力结构的方法包括形成覆盖半导体材料的第一应力诱导材料并形成覆盖第一应力诱导材料的间隔物。 使用间隔物作为蚀刻掩模蚀刻第一应力诱导材料，以形成多个第一应力诱导帽。 使用多个第一应力诱导盖作为蚀刻掩模蚀刻半导体材料。

公开(公告)号：US20100059852A1

公开(公告)日：2010-03-11

申请号：US12209056

申请日：2008-09-11

Applicant: Rohit PAL ,  David BROWN ,  Scott LUNING

Inventor： Rohit PAL ,  David BROWN ,  Scott LUNING

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device structure is provided. The method begins by providing a substrate having a layer of semiconductor material, a pad oxide layer overlying the layer of semiconductor material, and a pad nitride layer overlying the pad oxide layer. The method proceeds by selectively removing a portion of the pad nitride layer, a portion of the pad oxide layer, and a portion of the layer of semiconductor material to form an isolation trench. Then, the isolation trench is filled with a lower layer of isolation material, a layer of etch stop material, and an upper layer of isolation material, such that the layer of etch stop material is located between the lower layer of isolation material and the upper layer of isolation material. The layer of etch stop material protects the underlying isolation material during subsequent fabrication steps.

Abstract translation: 提供一种制造半导体器件结构的方法。 该方法开始于提供具有半导体材料层的衬底，覆盖在半导体材料层上的衬垫氧化物层和覆盖衬垫氧化物层的衬垫氮化物层。 该方法通过选择性地去除衬垫氮化物层的一部分，衬垫氧化物层的一部分和半导体材料层的一部分来形成隔离沟槽。 然后，隔离沟槽填充有较低层的隔离材料，一层蚀刻停止材料和上层隔离材料，使得该蚀刻停止材料层位于隔离材料的下层和上部隔离层之间 隔离材料层。 蚀刻停止材料层在随后的制造步骤期间保护下面的隔离材料。

公开(公告)号：US20090256201A1

公开(公告)日：2009-10-15

申请号：US12100598

申请日：2008-04-10

Applicant: Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

Inventor： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。