公开(公告)号：US20100308409A1

公开(公告)日：2010-12-09

申请号：US12480263

申请日：2009-06-08

申请人： Frank S. Johnson ,  Scott Luning ,  Michael J. Hargrove

发明人： Frank S. Johnson ,  Scott Luning ,  Michael J. Hargrove

IPC分类号： H01L27/088 ,  H01L21/308 ,  H01L21/31 ,  H01L21/8234

CPC分类号： H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7843

摘要： FinFET structures with fins having stress-inducing caps and methods for fabricating such FinFET structures are provided. In an exemplary embodiment, a method for forming stressed structures comprises forming a first stress-inducing material overlying a semiconductor material and forming spacers overlying the first stress-inducing material. The first stress-inducing material is etched using the spacers as an etch mask to form a plurality of first stress-inducing caps. The semiconductor material is etched using the plurality of first stress-inducing caps as an etch mask.

摘要翻译： 提供具有应力诱导帽的翅片的FinFET结构和用于制造这种FinFET结构的方法。 在示例性实施例中，用于形成应力结构的方法包括形成覆盖半导体材料的第一应力诱导材料并形成覆盖第一应力诱导材料的间隔物。 使用间隔物作为蚀刻掩模蚀刻第一应力诱导材料，以形成多个第一应力诱导帽。 使用多个第一应力诱导盖作为蚀刻掩模蚀刻半导体材料。

公开(公告)号：US08039349B2

公开(公告)日：2011-10-18

申请号：US12512814

申请日：2009-07-30

申请人： Michael J. Hargrove ,  Frank Scott Johnson ,  Scott Luning

发明人： Michael J. Hargrove ,  Frank Scott Johnson ,  Scott Luning

IPC分类号： H01L21/8234

CPC分类号： H01L21/26586 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7847 ,  H01L29/785

摘要： Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

摘要翻译： 提供了一种用于制造包括其上形成有多个凸起的晶体结构的基板的非平面半导体器件的方法的实施例。 在一个实施方案中，该方法包括以下步骤：将包含在多个凸起的晶体结构内的每个凸起的晶体结构的一部分非晶化，在多个凸起的晶体结构上形成牺牲应变层，以将应力施加到每个凸起晶体的非晶化部分 结构，退火所述非平面半导体器件以使应力存储状态下的每个凸起晶体结构的非晶化部分重结晶，以及去除所述牺牲应变层。

公开(公告)号：US07977174B2

公开(公告)日：2011-07-12

申请号：US12480269

申请日：2009-06-08

申请人： Scott Luning ,  Frank Scott Johnson ,  Michael J. Hargrove

发明人： Scott Luning ,  Frank Scott Johnson ,  Michael J. Hargrove

IPC分类号： H01L21/00

CPC分类号： H01L29/7843 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.

摘要翻译： 本文提供了制造具有应力诱导源极/漏极形成间隔物的FinFET结构和具有这种间隔物的FinFET结构的方法。 在一个实施例中，制造FinFET结构的方法包括制造覆盖半导体衬底的多个平行散热片。 每个翅片都有侧壁。 制造覆盖每个翅片的一部分的栅极结构。 栅极结构在翅片内具有侧壁并覆盖通道。 应力诱导侧壁间隔件围绕翅片的侧壁和门结构的侧壁形成。 应力诱导侧壁间隔物在通道内引起应力。 使用应力诱导侧壁间隔物和栅极结构作为注入掩模将第一导电率确定离子注入到鳍中，以在翅片内形成源区和漏区。

公开(公告)号：US08404592B2

公开(公告)日：2013-03-26

申请号：US12509918

申请日：2009-07-27

申请人： Scott Luning ,  Frank S. Johnson

发明人： Scott Luning ,  Frank S. Johnson

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/845 ,  H01L29/66795

摘要： Methods for fabricating semiconductor structures, such as fin structures of FinFET transistors, are provided. In one embodiment, a method comprises providing a semiconductor substrate and forming a plurality of mandrels overlying the semiconductor substrate. Each of the mandrels has sidewalls. L-shaped spacers are formed about the sidewalls of the mandrels. Each L-shaped spacer comprises a rectangular portion disposed at a base of a mandrel and an orthogonal portion extending from the rectangular portion. Each L-shaped spacer also has a spacer width. The orthogonal portions are removed from each of the L-shaped spacers leaving at least a portion of the rectangular portions. The semiconductor substrate is etched to form fin structures, each fin structure having a width substantially equal to the spacer width.

摘要翻译： 提供了制造半导体结构的方法，例如FinFET晶体管的鳍结构。 在一个实施例中，一种方法包括提供半导体衬底并形成覆盖半导体衬底的多个心轴。 每个心轴都有侧壁。 围绕心轴的侧壁形成L形间隔物。 每个L形间隔件包括设置在心轴的基部和从矩形部分延伸的正交部分的矩形部分。 每个L形间隔物也具有间隔物宽度。 从每个L形间隔件中取出正交部分，留下矩形部分的至少一部分。 蚀刻半导体衬底以形成鳍结构，每个鳍结构的宽度基本上等于间隔物宽度。

公开(公告)号：US08193592B2

公开(公告)日：2012-06-05

申请号：US12904662

申请日：2010-10-14

申请人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

发明人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

摘要翻译： 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US08148214B2

公开(公告)日：2012-04-03

申请号：US12360961

申请日：2009-01-28

申请人： Andrew M. Waite ,  Scott Luning

发明人： Andrew M. Waite ,  Scott Luning

IPC分类号： H01L21/00

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

摘要翻译： 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

公开(公告)号：US20110062498A1

公开(公告)日：2011-03-17

申请号：US12561685

申请日：2009-09-17

申请人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

发明人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

摘要翻译： 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

公开(公告)号：US07893493B2

公开(公告)日：2011-02-22

申请号：US11456326

申请日：2006-07-10

申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC分类号： H01L27/12 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

摘要： An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

摘要翻译： 中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中 衬垫，其中外延生长的硅基本上是无层错的。

公开(公告)号：US07674720B2

公开(公告)日：2010-03-09

申请号：US12131214

申请日：2008-06-02

申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

摘要翻译： 公开了用于提供用于混合表面取向结构的堆叠故障减少的外延生长的硅的方法。 在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫 并且在开口中外延生长硅。 由于底切产生的负斜率，硅片堆积层错误大大减少。

公开(公告)号：US07223662B2

公开(公告)日：2007-05-29

申请号：US11082122

申请日：2005-03-16

申请人： Thorsten Kammler ,  Scott Luning ,  Linda Black

发明人： Thorsten Kammler ,  Scott Luning ,  Linda Black

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/26506 ,  H01L21/28035 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772

摘要： By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

摘要翻译： 通过使用于形成隆起的漏极和源极区域以及下部衬底的一部分或仅仅衬底的表面区域（在生长硅覆盖层之前）的选择性外延生长的硅层基本上非晶化，位于 可以显着减少生长的硅层和初始衬底表面。 因此，可以抑制诸如电荷载体吸杂或产生掺杂剂的扩散路径的有害影响。