公开(公告)号：US20060079056A1

公开(公告)日：2006-04-13

申请号：US11247412

申请日：2005-10-11

Applicant: Young-Pil Kim ,  Sun-Ghil Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  In-Soo Jung

Inventor： Young-Pil Kim ,  Sun-Ghil Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  In-Soo Jung

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/78

Abstract: A semiconductor structure including a SiGe layer and a method of fabricating the same are provided. The structure includes a silicon layer heavily doped with impurities. A SiGe layer is disposed on the silicon layer. A strained silicon layer is disposed on the SiGe layer. The impurities may be boron. The boron in the silicon layer may have a concentration of 1016 to 1020/cm3. Boron in the SiGe layer, diffused from the silicon substrate or directly doped, may suppress movement of misfit dislocation occurring in the SiGe layer toward the surface, thereby reducing a threading dislocation density near the surface of the strained silicon layer.

Abstract translation: 提供了包括SiGe层的半导体结构及其制造方法。 该结构包括重掺杂杂质的硅层。 SiGe层设置在硅层上。 应变硅层设置在SiGe层上。 杂质可以是硼。 硅层中的硼可以具有10 16至10 20 / cm 3的浓度。 在SiGe层中从硅衬底扩散或直接掺杂的硼可以抑制SiGe层中发生的失配位错的移动朝向表面，由此降低应变硅层表面附近的穿透位错密度。

公开(公告)号：US20060057821A1

公开(公告)日：2006-03-16

申请号：US11208490

申请日：2005-08-22

Applicant: Sun-Ghil Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Deok-Hyung Lee ,  In-Soo Jung ,  Young-Eun Lee

Inventor： Sun-Ghil Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Deok-Hyung Lee ,  In-Soo Jung ,  Young-Eun Lee

IPC: H01L21/30

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L21/32135 ,  H01L29/165 ,  H01L29/66628

Abstract: Methods of etching a semiconductor substrate may include providing a first gas that is chemically reactive with respect to the semiconductor substrate, and while providing the first gas, providing a second gas different than the first gas. More particularly, a molecule of the second gas may include a hydrogen atom, and the second gas may lower a temperature at which the first gas chemically reacts with the semiconductor substrate. The mixture of the first and second gases may be provided adjacent the semiconductor substrate to etch the semiconductor substrate.

Abstract translation: 蚀刻半导体衬底的方法可以包括提供相对于半导体衬底具有化学反应性的第一气体，并且在提供第一气体的同时，提供不同于第一气体的第二气体。 更具体地，第二气体的分子可以包括氢原子，第二气体可以降低第一气体与半导体衬底发生化学反应的温度。 第一和第二气体的混合物可以设置在邻近半导体衬底处以蚀刻半导体衬底。

公开(公告)号：US20050248035A1

公开(公告)日：2005-11-10

申请号：US11092524

申请日：2005-03-29

Applicant: Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Sun-Ghil Lee ,  In-Soo Jung ,  Young-Eun Lee ,  Deok-Hyung Lee

Inventor： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Sun-Ghil Lee ,  In-Soo Jung ,  Young-Eun Lee ,  Deok-Hyung Lee

IPC: H01L21/28 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/52 ,  H01L27/06 ,  H01L29/40

CPC classification number: H01L29/7842 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/0688

Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.

Abstract translation: 半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。 该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。 该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

公开(公告)号：US08415224B2

公开(公告)日：2013-04-09

申请号：US13184318

申请日：2011-07-15

Applicant: Sung-Woo Hyun ,  Yu-Gyun Shin ,  Sun-Ghil Lee ,  Hong-Sik Yoon

Inventor： Sung-Woo Hyun ,  Yu-Gyun Shin ,  Sun-Ghil Lee ,  Hong-Sik Yoon

IPC: H01L21/331 ,  H01L21/76

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

Abstract translation: 提供一种制造半导体器件和半导体器件的方法。 该方法包括制造半导体器件的方法，该半导体器件包括提供具有限定在其中的第一半导体器件区域和第二半导体器件区域的半导体衬底，在第一半导体器件区域中形成第一栅极结构，在第二半导体中形成第二栅极结构 形成与所述第一栅极结构的第一侧相邻的第一沟槽，形成邻近所述第二栅极结构的第一侧的第二沟槽，以及在所述第一沟槽中形成第一半导体图案并形成第二半导体图案 第二沟槽，其中第一和第二沟槽彼此具有不同的横截面形状。

公开(公告)号：US20130005096A1

公开(公告)日：2013-01-03

申请号：US13368584

申请日：2012-02-08

Applicant: Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

Inventor： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/78

Abstract: A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

公开(公告)号：US20120299154A1

公开(公告)日：2012-11-29

申请号：US13459740

申请日：2012-04-30

Applicant: Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

Inventor： Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

IPC: H01L29/00 ,  H01L21/336 ,  H01L21/04

CPC classification number: H01L29/6659 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract translation: 通过在基板上形成第一绝缘层，在第一绝缘层上进行第一次氮化，形成第二绝缘层，依次进行第一和第二退火，制造具有改善的负偏压温度不稳定寿命特性的半导体器件 第二绝缘层以形成第三绝缘层，其中所述第二退火在比所述第一退火更高的温度和不同的气体下进行。 在第三绝缘层上进行第二次氮化，以形成第四绝缘层，并且在第四绝缘层上顺序的第三和第四退火形成第五绝缘层。 第三退火在比第一退火更高的温度下进行，第四退火在比第二退火更高的温度下进行，并且具有比第三退火不同的气体。

公开(公告)号：US20120049285A1

公开(公告)日：2012-03-01

申请号：US13184318

申请日：2011-07-15

Applicant: Sung-Woo Hyun ,  Yu-Gyun Shin ,  Sun-Ghil Lee ,  Hong-Sik Yoon

Inventor： Sung-Woo Hyun ,  Yu-Gyun Shin ,  Sun-Ghil Lee ,  Hong-Sik Yoon

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

Abstract translation: 提供一种制造半导体器件和半导体器件的方法。 该方法包括制造半导体器件的方法，该半导体器件包括提供具有限定在其中的第一半导体器件区域和第二半导体器件区域的半导体衬底，在第一半导体器件区域中形成第一栅极结构，在第二半导体中形成第二栅极结构 形成与所述第一栅极结构的第一侧相邻的第一沟槽，形成邻近所述第二栅极结构的第一侧的第二沟槽，以及在所述第一沟槽中形成第一半导体图案并形成第二半导体图案 第二沟槽，其中第一和第二沟槽彼此具有不同的横截面形状。

公开(公告)号：US20110049596A1

公开(公告)日：2011-03-03

申请号：US12728396

申请日：2010-03-22

Applicant: Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

Inventor： Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

IPC: H01L27/108 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L21/76843 ,  H01L21/28525 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.

Abstract translation: 提供了包括半导体衬底，包括暴露半导体衬底的接触孔的绝缘层和填充接触孔的多晶硅层的半导体器件。 多晶硅层掺杂有杂质，并且包括杂质扩散防止层。 在半导体器件中，包含在多晶硅层中的杂质不会由于杂质扩散层而扩散到绝缘层和半导体衬底中。

公开(公告)号：US07842566B2

公开(公告)日：2010-11-30

申请号：US12000071

申请日：2007-12-07

Applicant: Deok-Hyung Lee ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Si-Young Choi

Inventor： Deok-Hyung Lee ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Si-Young Choi

IPC: H01L21/8234

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66795

Abstract: A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of the semiconductor fin.

Abstract translation: FinFET可以包括具有顶表面和具有不同晶面的侧壁的半导体鳍片。 顶表面和侧壁上的栅介电层具有不同的厚度。 栅电极跨过半导体鳍片的顶表面和侧壁形成在栅介质层上。

公开(公告)号：US07799648B2

公开(公告)日：2010-09-21

申请号：US12478345

申请日：2009-06-04

Applicant: Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

Inventor： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

IPC: H01L21/336

CPC classification number: C30B29/06 ,  C30B15/00

Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

Abstract translation: 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。