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41.发明申请Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events 有权处理器睡眠和唤醒事件的硬件自动性能状态转换系统公开(公告)号：US20110252251A1
公开(公告)日：2011-10-13
申请号：US12756006
申请日：2010-04-07
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
摘要翻译： 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。
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公开(公告)号：US20110010504A1
公开(公告)日：2011-01-13
申请号：US12500747
申请日：2009-07-10
申请人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
发明人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0638 , G06F3/0673 , G06F12/0802 , G06F12/0831 , G06F12/0848 , G06F12/0853 , G06F12/0864 , G06F12/0877 , G06F12/125 , G06F2212/1021 , G06F2212/2515 , G06F2212/282 , G06F2212/601 , G06F2212/62 , Y02D10/13
摘要： In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.
摘要翻译： 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。
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公开(公告)号：US06972768B2
公开(公告)日：2005-12-06
申请号：US10997103
申请日：2004-11-24
CPC分类号： G06T11/40 , G09G5/393 , G09G2360/122
摘要： A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles. The rasterization process proceeds bottom-up completing at each lower level before completing at higher levels. In this way, the present invention provides a method for rasterizing graphics primitives that accesses memory tiles in an orderly fashion. This reduces page misses within the frame buffer and enhances graphics performance.
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公开(公告)号：US06611272B1
公开(公告)日：2003-08-26
申请号：US09145516
申请日：1998-09-02
IPC分类号： G09G539
CPC分类号： G06T11/40 , G09G5/393 , G09G2360/122
摘要： A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles. The rasterization process proceeds bottom-up completing at each lower level before completing at higher levels. In this way, the present invention provides a method for rasterizing graphics primitives that accesses memory tiles in an orderly fashion. This reduces page misses within the frame buffer and enhances graphics performance.
摘要翻译： 提供了一种有效地光栅化图形的方法和装置。 该方法旨在与提供快速基于瓦片的寻址的帧缓冲器组合使用。 在这种环境中，帧缓冲存储器位置被组织成层次结构。 对于这种层次结构，较小的低级瓦片组合形成较大的中间瓦片。 中层瓷砖结合形成高级瓷砖。 瓦片层次结构可以被扩展以包括更多的级别，或者折叠成包括较少的级别。 通过选择起始顶点来对图形原语进行光栅化。 然后将包含起始顶点的低级瓦片光栅化。 然后将与包含在与起始顶点相同的中间瓦片中的剩余低级瓦片光栅化。 栅格化继续与包含在与起始顶点相同的高级平铺中的中间层块。 通过对其组件低级图块进行光栅化，可以对这些中间级的图块进行栅格化。 在更高级别完成之前，光栅化过程在每个较低级别进行自下而上的完成。 以这种方式，本发明提供了一种用于光栅化以有序方式访问存储器块的图形基元的方法。 这减少了帧缓冲区内的页错误并提高了图形性能。
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公开(公告)号：US6075546A
公开(公告)日：2000-06-13
申请号：US967085
申请日：1997-11-10
CPC分类号： G06F9/3877 , G06F9/3879
摘要： A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in the memory of the host computer system. Each packet descriptor includes a pointer to a region of memory known as a packet buffer. Each packet descriptor also includes a ready variable. To pass commands to the graphics processor, a graphics process selects a packet buffer. The packet buffer must have a ready variable that is set to the value false. After selection of the appropriate packet descriptor, the graphics process writes the desired commands into the packet descriptor associated with the selected packet descriptor. The graphics process then sets the ready variable included in the selected packet descriptor to true. The graphics processor traverses the queues of packet descriptors. For each packet descriptor encountered, the graphics processor tests the included ready variable. If the ready variable is set to true, the graphics processor executes the commands included in the associated packet buffer. After completing these commands, the graphics processor sets the ready variable to false. In this way, the present invention allows the host and graphics processors to execute in parallel and allows commands to be transferred to the graphics processor without the use of a system call.
摘要翻译： 提供了一种用于将命令传送到图形处理器的方法和装置。 该方法和装置旨在用于具有可被主处理器和图形处理器寻址的存储器的主计算机系统中。 分组描述符的一个或多个队列被维护在主计算机系统的存储器中。 每个分组描述符包括指向被称为分组缓冲器的存储器区域的指针。 每个数据包描述符还包括一个ready变量。 为了将命令传递到图形处理器，图形进程选择一个数据包缓冲区。 包缓冲区必须有一个ready变量，设置为false值。 在选择适当的分组描述符之后，图形过程将所需命令写入与所选分组描述符相关联的分组描述符中。 然后，图形处理将包含在所选数据包描述符中的就绪变量设置为true。 图形处理器遍历数据包描述符的队列。 对于遇到的每个数据包描述符，图形处理器会测试包含的就绪变量。 如果ready变量设置为true，则图形处理器执行包括在相关联的分组缓冲器中的命令。 完成这些命令后，图形处理器将ready变量设置为false。 以这种方式，本发明允许主机和图形处理器并行执行，并且允许将命令传送到图形处理器而不使用系统调用。
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公开(公告)号：US09176913B2
公开(公告)日：2015-11-03
申请号：US13226718
申请日：2011-09-07
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time port of a memory controller. The coherence switch routes non-coherent traffic to a non-real time port of the memory controller. The coherence switch can also dynamically switch traffic between the two paths. The routing of traffic can be configured via a configuration register, and while software can initiate an update to the configuration register, the actual coherence switch hardware will implement the update. Software can write to a software-writeable copy of the configuration register to initiate an update to the flow path to memory for a transaction identifier. The coherence switch detects the update to the software-writeable copy, and then the coherence switch updates the working copy of the configuration register and implements the new routing.
摘要翻译： 用于将SoC中的业务从I / O设备路由到存储器的系统，装置和方法。 相干切换器将相干流量通过处理器复合体上的一致端口路由到存储器控制器的实时端口。 相干切换将非相干流量路由到存储器控制器的非实时端口。 相干切换器还可以动态地切换两条路径之间的流量。 流量路由可以通过配置寄存器配置，而软件可以启动对配置寄存器的更新，实际的相干交换机硬件将实现更新。 软件可以写入配置寄存器的可写入软件的副本，以启动对事务标识符的存储器流程的更新。 相干开关检测到软件可写入副本的更新，然后相干开关更新配置寄存器的工作副本并实现新的路由。
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公开(公告)号：US08675004B2
公开(公告)日：2014-03-18
申请号：US12685171
申请日：2010-01-11
IPC分类号： G06F13/372
摘要： A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.
摘要翻译： 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。
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公开(公告)号：US08610830B2
公开(公告)日：2013-12-17
申请号：US12317811
申请日：2008-12-30
IPC分类号： H04B1/00
摘要： A media processing system with an improved method and device for rotating a video image is provided. Embodiments of the media processing system include a video decoder with the ability to output decoded video in a landscape or portrait orientation. In some embodiments, the video output orientation is based on the physical orientation of the display as indicated by an electronic sensor.
摘要翻译： 提供了一种具有用于旋转视频图像的改进方法和装置的媒体处理系统。 媒体处理系统的实施例包括具有以横向或纵向方向输出解码视频的能力的视频解码器。 在一些实施例中，视频输出取向基于如电子传感器所指示的显示器的物理取向。
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公开(公告)号：US08489376B2
公开(公告)日：2013-07-16
申请号：US12860668
申请日：2010-08-20
申请人： Marc A. Schaub , Shun Wai Go , Sukalpa Biswas , Timothy J. Millet
发明人： Marc A. Schaub , Shun Wai Go , Sukalpa Biswas , Timothy J. Millet
CPC分类号： G06F17/5022
摘要： In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.
摘要翻译： 在一个实施例中，可以使用控制器的寄存器传送级（RTL）表示（或其他周期精确表示）以及到控制器的通信结构中的电路来创建模型。 请求源可以被交易者代替，交易者可以生成事务来测试结构和控制器的性能。 因此，在该实施例中，仅需要控制器和结构电路的设计来建模性能。 在一个实施例中，至少一些交易者可以是尝试模拟相应请求源的操作的行为交易者。 在一些实施例中，其他交易者可以是统计分布。 在一个实施例中，事务处理器可以包括交易发生器（例如行为或统计）和协议转换器，其被配置为在交易者连接到该结构的点处将生成的交易转换为使用中的通信协议。
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50.发明授权System and method for masking visual compression artifacts in decoded video streams 有权用于掩蔽解码视频流中视觉压缩伪影的系统和方法公开(公告)号：US08345775B2
公开(公告)日：2013-01-01
申请号：US12102714
申请日：2008-04-14
申请人： Haitao Guo , Sally Fung , Timothy J. Millet
发明人： Haitao Guo , Sally Fung , Timothy J. Millet
IPC分类号： H04N7/12
CPC分类号： H04N19/86
摘要： A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer.
摘要翻译： 提供了一种用于处理解码的视频数据以掩盖视频压缩产生的视觉压缩伪影的技术。 根据该技术，提供了一个硬件块，用于产生并将随机噪声添加到解码的视频流中。 在一个实施例中，为解码视频数据的每个像素生成随机数，并与一个或多个阈值进行比较以确定阈值范围。 在这样的实施例中，基于阈值比较选择噪声加数值并与当前像素相加。 虽然本技术可能不能消除压缩伪影，但是随机噪声的增加使得压缩伪影对人眼不那么显着，因此对于观看者而言更加美观。
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