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    Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)
    43.
    发明授权
    Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO) 有权
    实现增强型SRAM读取性能排序环形振荡器（PSRO）的方法和装置

    公开(公告)号：US07480170B1

    公开(公告)日：2009-01-20

    申请号：US11782808

    申请日：2007-07-25

    申请人： Chad Allen Adams ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Kirk David Peterson

    发明人： Chad Allen Adams ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Kirk David Peterson

    IPC分类号： G11C11/40

    CPC分类号： G11C11/413 ,  G11C11/41 ,  G11C11/419 ,  G11C2029/0403

    摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.

    摘要翻译： 包括静态随机存取存储器（SRAM）单元的方法和装置实现增强型SRAM读取性能排序环形振荡器（PSRO）。 一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。 例如，静态锁存器的补码侧连接到电源。 多个SRAM单元组装在一起以形成SRAM基块。 多个SRAM基块被连接在一起以形成SRAM读取PSRO。

    Split local and continuous bitline requiring fewer wires
    46.
    发明授权
    Split local and continuous bitline requiring fewer wires 有权
    拆分本地和连续的位线，需要更少的电线

    公开(公告)号：US06741493B1

    公开(公告)日：2004-05-25

    申请号：US10289804

    申请日：2002-11-07

    申请人： Todd Alan Christensen ,  Peter Thomas Freiburger

    发明人： Todd Alan Christensen ,  Peter Thomas Freiburger

    IPC分类号： G11C1100

    CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/18

    摘要： An improved memory device has a reduced number of wires for carrying local write signals. The improved memory device includes an array of memory cells. A plurality of local true bitlines is coupled to the array of memory cells. A plurality of continuous complement bitlines is coupled to the array of memory cells. The memory device also includes a plurality of write circuits. At least one write circuit is coupled to at least one continuous complement bitline and at least one local true bitline, receives information on a data input from the continuous complement bitline, and controls the local true bitline. At least one local write line is coupled to at least two of the write circuits for providing a write enable signal to the two write circuits.

    摘要翻译： 改进的存储器件具有减少数量的用于承载本地写入信号的导线。 改进的存储器件包括存储器单元的阵列。 多个本地真实位线耦合到存储器单元阵列。 多个连续补码位线耦合到存储器单元阵列。 存储装置还包括多个写入电路。 至少一个写入电路耦合到至少一个连续补码位线和至少一个本地真实位线，从连续补码位线接收关于数据输入的信息，并控制局部真实位线。 至少一个本地写入线耦合到至少两个写入电路，以向两个写入电路提供写入使能信号。

    Method for implementing SOI transistor source connections using buried dual rail distribution
    48.
    发明授权
    Method for implementing SOI transistor source connections using buried dual rail distribution 失效
    使用埋地双轨分布实现SOI晶体管源连接的方法

    公开(公告)号：US06498057B1

    公开(公告)日：2002-12-24

    申请号：US10092748

    申请日：2002-03-07

    申请人： Todd Alan Christensen ,  John Edward Sheets, II ,  Gregory John Uhlmann

    发明人： Todd Alan Christensen ,  John Edward Sheets, II ,  Gregory John Uhlmann

    IPC分类号： H01L2100

    CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84

    摘要： Methods and silicon-on-Insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rall distribution. A SOI semiconductor structure Includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined burled conduction layer to be connected to a SOI transistor source, and an Intermediate conduction layer between the SOI transistor and the predefined buried conduction layer, A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silcide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An Insulator is disposed between the second hole and the intermediate conduction layer. A conductor Is deposited in the first and second holes to create a transistor source connection to the predefined burled conduction layer In the SOI semiconductor structure.

    摘要翻译： 提供了方法和绝缘体上硅（SOI）半导体结构，用于实现使用掩埋双球面分布的SOI晶体管器件的晶体管源极连接。 SOI半导体结构包括具有覆盖SOI晶体管源的硅化物层的SOI晶体管，要连接到SOI晶体管源的预定义的烧制导电层，以及SOI晶体管和预定义的掩埋导电层之间的中间导电层，A第一 用于与局部互连的晶体管源极连接的孔在SOI半导体结构中被各向异性地蚀刻到覆盖SOI晶体管源的硅化物层。 与局部互连孔对准的第二孔通过SOI半导体结构被各向异性蚀刻到预定义的掩埋导电层。 绝缘体设置在第二孔和中间导电层之间。 在SOI半导体结构中，导体沉积在第一和第二孔中以产生到预定义的透明导电层的晶体管源极连接。

    Integrated circuit having integral decoupling capacitor
    49.
    发明授权
    Integrated circuit having integral decoupling capacitor 失效
    具有积分去耦电容器的集成电路

    公开(公告)号：US06303457B1

    公开(公告)日：2001-10-16

    申请号：US08890047

    申请日：1997-07-09

    申请人： Todd Alan Christensen ,  John Edward Sheet, II

    发明人： Todd Alan Christensen ,  John Edward Sheet, II

    IPC分类号： H01L2120

    CPC分类号： H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention is a decoupling capacitor for an integrated circuit. The integrated circuit has a final metal layer which includes a power bus. The decoupling capacitor comprises a dielectric film disposed over the final metal layer and a conductive film disposed over the dielectric layer, whereby capacitance may be provided in the dielectric layer.

    摘要翻译： 本发明是用于集成电路的去耦电容器。 该集成电路具有包括电源总线的最终金属层。 去耦电容器包括设置在最终金属层上的电介质膜和设置在介电层上的导电膜，由此可以在电介质层中提供电容。