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    Semiconductor integrated circuit device and method for testing the same
    42.
    发明申请
    Semiconductor integrated circuit device and method for testing the same 有权
    半导体集成电路器件及其测试方法

    公开(公告)号：US20050047236A1

    公开(公告)日：2005-03-03

    申请号：US10928366

    申请日：2004-08-30

    申请人： Masanori Shirahama ,  Masashi Agata ,  Toshiaki Kawasaki ,  Ryuji Nishihara

    发明人： Masanori Shirahama ,  Masashi Agata ,  Toshiaki Kawasaki ,  Ryuji Nishihara

    IPC分类号： G11C16/02 ,  G11C7/06 ,  G11C7/10 ,  G11C16/06 ,  G11C7/00 ,  G11C29/00

    CPC分类号： G11C7/1096 ,  G11C7/062 ,  G11C7/1078

    摘要： A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.

    摘要翻译： 一种半导体集成电路器件，包括：第一和第二非易失性存储元件; 第一放大器，用于放大来自第一非易失性存储器元件的输出信号以输出放大的信号; 以及第二放大器，用于向第一放大器输出通过放大来自第二非易失性存储元件的输出信号而产生的控制信号。 第二放大器基于存储在第二非易失性存储器元件中的数据，将来自第一放大器的输出信号固定在高电位或低电位。

    Semiconductor device incorporating circuit for generating control clock in accordance with external clock frequency
    43.
    发明授权
    Semiconductor device incorporating circuit for generating control clock in accordance with external clock frequency 失效
    具有根据外部时钟频率产生控制时钟的电路的半导体器件

    公开(公告)号：US06448826B1

    公开(公告)日：2002-09-10

    申请号：US09790501

    申请日：2001-02-23

    申请人： Tsukasa Ooishi ,  Toshiaki Kawasaki

    发明人： Tsukasa Ooishi ,  Toshiaki Kawasaki

    IPC分类号： H03L706

    CPC分类号： H03L7/0805 ,  G06F1/12 ,  H03K5/133 ,  H03K5/156 ,  H03K2005/00039 ,  H03K2005/00058 ,  H03K2005/00195 ,  H03K2005/00208 ,  H03L7/00 ,  H03L7/0812 ,  H03L7/089

    摘要： A semiconductor device according to the present invention operates in response to a control clock generated by a control clock generating circuit. The control clock generating circuit includes a DLL circuit detecting an external clock period by a synchronous operation, a reference clock pulse generating circuit activated in synchronization with an external clock to generate a reference dock pulse having a pulse width in accordance with the external clock period, a delay circuit delaying stepwise the reference clock pulse per unit delay time in accordance with the external clock period, and an internal control clock generating circuit setting activation and inactivation timing of the control clock based on the delayed clock pulse.

    摘要翻译： 根据本发明的半导体器件响应于由控制时钟发生电路产生的控制时钟而工作。 控制时钟产生电路包括通过同步操作检测外部时钟周期的DLL电路，与外部时钟同步激活的基准时钟脉冲发生电路，以产生具有与外部时钟周期相对应的脉冲宽度的参考基准脉冲， 延迟电路根据外部时钟周期逐步延迟每单位延迟时间的参考时钟脉冲，以及内部控制时钟产生电路，基于延迟的时钟脉冲设置控制时钟的激活和失活定时。

    Semiconductor integrated circuit
    44.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5881012A

    公开(公告)日：1999-03-09

    申请号：US633684

    申请日：1996-04-17

    申请人： Toshiaki Kawasaki ,  Akinori Shibayama

    发明人： Toshiaki Kawasaki ,  Akinori Shibayama

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  H03K17/06 ,  H03K3/353

    CPC分类号： G11C5/145 ,  H03K17/063

    摘要： A frequency switching circuit is controlled by a low address strobe signal XRAS. A sub-boosted power supply generating circuit is driven at a low frequency generated by a first oscillating circuit during the standby of a DRAM, and at a high frequency generated by a second oscillating circuit during the operation of the DRAM. The sub-boosted power supply generating circuit is driven in a shorter cycle during the operation than during the standby. Consequently, charges are supplied to a booster power source to boost the voltage level thereof. Accordingly, even if the period of the operation state is increased, a drop in voltage level of the boosted power supply caused by a transistor off leak current and a junction leak current can be controlled. Thus, the malfunction of a circuit can be prevented from occurring due to the drop in voltage level of the boosted power supply. The drop in voltage level of the boosted power supply can be controlled during the operation of the DRAM so that it is possible to implement a boosted power supply generating circuit which can prevent the malfunction of the circuit from occurring.

    摘要翻译： 频率切换电路由低地址选通信号XRAS控制。 次级升压电源发生电路在DRAM的待机期间由第一振荡电路产生的低频驱动，并且在DRAM的操作期间由第二振荡电路产生的高频驱动。 次升压电源发生电路在操作期间以比待机期间更短的周期被驱动。 因此，电荷被提供给升压电源以升高其电压电平。 因此，即使操作状态的周期增加，可以控制由晶体管断开漏电流和结漏电流引起的升压电源的电压电平的下降。 因此，可以防止由于升压电源的电压电平的下降而发生电路的故障。 可以在DRAM的操作期间控制升压电源的电压电平的下降，使得可以实现可以防止电路故障发生的升压电源产生电路。

    SEMICONDUCTOR DEVICE
    48.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120169402A1

    公开(公告)日：2012-07-05

    申请号：US13417548

    申请日：2012-03-12

    申请人： TOSHIAKI KAWASAKI ,  YASUHIRO AGATA ,  MASANORI SHIRAHAMA ,  TOSHIHIRO KOUGAMI ,  KATSUYA ARAI

    发明人： TOSHIAKI KAWASAKI ,  YASUHIRO AGATA ,  MASANORI SHIRAHAMA ,  TOSHIHIRO KOUGAMI ,  KATSUYA ARAI

    IPC分类号： H01H37/76

    CPC分类号： H01L27/0207 ,  G11C17/18 ,  H01L23/5256 ,  H01L27/0288 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

    摘要翻译： 半导体器件包括电熔丝电路和程序保护电路。 电熔丝电路包括串联连接在一起的一个熔丝元件和一个晶体管，并放置在一个程序电源和一个接地之间，以及控制部分。 程序保护电路与电熔丝电路并联在程序电源和接地之间。 当在程序电源和接地之间施加浪涌电压时，上述结构允许一部分浪涌电流可以流过程序保护电路。

    Nonvolatile semiconductor memory device
    49.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08094498B2

    公开(公告)日：2012-01-10

    申请号：US12792295

    申请日：2010-06-02

    申请人： Yasue Yamamoto ,  Masanori Shirahama ,  Yasuhiro Agata ,  Toshiaki Kawasaki

    发明人： Yasue Yamamoto ,  Masanori Shirahama ,  Yasuhiro Agata ,  Toshiaki Kawasaki

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0441 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.

    摘要翻译： 在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器 擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。 这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。

    Nonvolatile semiconductor memory device
    50.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07623380B2

    公开(公告)日：2009-11-24

    申请号：US11526057

    申请日：2006-09-25

    申请人： Yasue Yamamoto ,  Yasuhiro Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki

    发明人： Yasue Yamamoto ,  Yasuhiro Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11558

    摘要： A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.

    摘要翻译： 用于通过在浮动栅极中累积电荷来存储数据的非易失性半导体存储器件包括共享浮置栅极的多个MOS晶体管。 在器件中，在写入期间使用PMOS耦合并且在擦除期间使用n型耗尽MOS（DMOS）耦合。 与传统的三晶体管非易失性存储元件相比，通过PMOS将沟道反转电容耦合用于n型DMOS的耗尽电容的写入和耦合用于擦除，从而增加擦除速度而不增加面积。