公开(公告)号：US20070096200A1

公开(公告)日：2007-05-03

申请号：US11642658

申请日：2006-12-21

Applicant: Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  H01L21/2815 ,  H01L29/40114 ,  H01L29/42324

Abstract: A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

Abstract translation: 一种用于在用于高速RAM应用的浮动栅极的两侧上制造侧壁控制栅极的自对准导电间隔物工艺，其可以很好地限定侧壁控制栅极的尺寸和轮廓。 在电介质层上形成导电层，以覆盖图案化在半导体衬底上的浮动栅极。 在与浮动栅极的侧壁相邻的导电层上形成氧化物间隔物。 在导电层上进行各向异性蚀刻处理并使用氧化物间隔物作为硬掩模，导电间隔物在浮栅的两侧制造，用作侧壁控制栅极。

公开(公告)号：US07176084B2

公开(公告)日：2007-02-13

申请号：US11148342

申请日：2005-06-09

Applicant: Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/4763 ,  H01L21/3205 ,  H01L21/461 ,  H01L21/302

CPC classification number: H01L29/7881 ,  H01L21/2815 ,  H01L21/28273 ,  H01L29/42324

Abstract: A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

公开(公告)号：US09953885B2

公开(公告)日：2018-04-24

申请号：US12843693

申请日：2010-07-26

Applicant: Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

Inventor： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC: H01L21/76 ,  H01L21/84 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

公开(公告)号：US09484462B2

公开(公告)日：2016-11-01

申请号：US12766233

申请日：2010-04-23

Applicant: Feng Yuan ,  Hung-Ming Chen ,  Tsung-Lin Lee ,  Chang-Yun Chang ,  Clement Hsingjen Wann

Inventor： Feng Yuan ,  Hung-Ming Chen ,  Tsung-Lin Lee ,  Chang-Yun Chang ,  Clement Hsingjen Wann

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/308 ,  H01L29/7851 ,  H01L29/7853

Abstract: An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.

Abstract translation: 鳍状场效应晶体管的示例性结构包括：包括主表面的衬底; 多个翅片结构，从所述基底的主表面突出，其中每个翅片结构包括在翅片结构的侧壁与主表面成85度角的过渡位置处分离的上部和下部 ，其中所述上部具有基本上垂直于所述基底的主表面的侧壁和具有第一宽度的顶表面，其中所述下部具有在所述上部的相对侧上的锥形侧壁和具有第二宽度的基部 宽度大于第一宽度; 以及在翅片结构之间的多个隔离结构，其中每个隔离结构从基板的主表面延伸到过渡位置上方的点。

公开(公告)号：US08847293B2

公开(公告)日：2014-09-30

申请号：US13411304

申请日：2012-03-02

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Wei-Jen Lai

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Wei-Jen Lai

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L27/0886 ,  H01L21/28088 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823431 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

Abstract translation: 描述了一种半导体器件及其制造方法，其包括具有顶表面的翅片和第一和第二侧向侧壁的基板。 可以在翅片的顶表面上形成硬掩模层（例如，提供双栅极器件）。 栅极电介质层和功函数金属层形成在鳍的第一和第二侧壁上。 在翅片的第一和第二侧壁上的功函数金属层上形成硅化物层。 硅化物层可以是完全硅化的层，并且可以对设置在鳍中的器件的沟道区域提供应力。

公开(公告)号：US08623718B2

公开(公告)日：2014-01-07

申请号：US13247570

申请日：2011-09-28

Applicant: Feng Yuan ,  Tsung-Lin Lee ,  Shao-Ming Yu ,  Clement Hsingjen Wann

Inventor： Feng Yuan ,  Tsung-Lin Lee ,  Shao-Ming Yu ,  Clement Hsingjen Wann

IPC: H01L21/00

CPC classification number: H01L29/66803

Abstract: In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.

Abstract translation: 在形成FinFET的方法中，形成光致抗蚀剂以覆盖晶片中的第一半导体鳍片，其中与第一半导体鳍片相邻的第二半导体鳍片不被光致抗蚀剂覆盖。 第一半导体鳍片和第二半导体鳍片之间的平行于第一和第二半导体鳍片的光刻胶的边缘比第二半导体鳍片更靠近第一半导体鳍片。 进行倾斜注入以在第二半导体鳍片中形成轻掺杂的源极/漏极区域，其中第一倾斜注入从第二半导体鳍片向第一半导体鳍片倾斜。

公开(公告)号：US20130285153A1

公开(公告)日：2013-10-31

申请号：US13487860

申请日：2012-06-04

Applicant: Tsung-Lin LEE ,  Chih Chieh YEH ,  Feng YUAN ,  Cheng-Yi PENG ,  Clement Hsingjen WANN

Inventor： Tsung-Lin LEE ,  Chih Chieh YEH ,  Feng YUAN ,  Cheng-Yi PENG ,  Clement Hsingjen WANN

IPC: H01L27/092 ,  H01L21/20 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/7848

Abstract: An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

Abstract translation: 用于场效应晶体管（FET）的示例性结构包括：硅衬底，其包括第一表面; 在所述第一表面上的通道部分，其中所述通道部分具有​​在所述第一表面上方的第一高度处的第二表面和平行于第一表面的长度; 以及沿沟道部分的长度围绕沟道部分的两个源极/漏极（S / D）区域，其中两个S / D区域包括SiGe，Ge，Si，SiC，GeSn，SiGeSn，SiSn， 或III-V材料。

公开(公告)号：US20130078772A1

公开(公告)日：2013-03-28

申请号：US13247570

申请日：2011-09-28

Applicant: Feng Yuan ,  Tsung-Lin Lee ,  Shao-Ming Yu ,  Clement Hsingjen Wann

Inventor： Feng Yuan ,  Tsung-Lin Lee ,  Shao-Ming Yu ,  Clement Hsingjen Wann

IPC: H01L21/336

CPC classification number: H01L29/66803

Abstract: In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.

Abstract translation: 在形成FinFET的方法中，形成光致抗蚀剂以覆盖晶片中的第一半导体鳍片，其中与第一半导体鳍片相邻的第二半导体鳍片不被光致抗蚀剂覆盖。 第一半导体鳍片和第二半导体鳍片之间的平行于第一和第二半导体鳍片的光刻胶的边缘比第二半导体鳍片更靠近第一半导体鳍片。 进行倾斜注入以在第二半导体鳍片中形成轻掺杂的源极/漏极区域，其中第一倾斜注入从第二半导体鳍片向第一半导体鳍片倾斜。

公开(公告)号：US20130075818A1

公开(公告)日：2013-03-28

申请号：US13243723

申请日：2011-09-23

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Clement Hsingjen Wann

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Clement Hsingjen Wann

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region.

Abstract translation: 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括衬底和设置在衬底上的3D结构。 半导体器件还包括设置在3D结构上的电介质层，设置在电介质层上的WFMG层，以及设置在WFMG层上的栅极结构。 栅极结构横穿3D结构并分离3D结构的源极区域和漏极区域。 源极和漏极区域在其间限定沟道区域。 栅极结构在沟道区域中引起应力。

公开(公告)号：US20120100673A1

公开(公告)日：2012-04-26

申请号：US13343586

申请日：2012-01-04

Applicant: Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

Inventor： Ming-Feng Shieh ,  Tsung-Lin Lee ,  Chang-Yun Chang

IPC: H01L21/336

CPC classification number: H01L21/823431 ,  H01L21/845

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.

Abstract translation: 形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。