公开(公告)号：US20090267638A1

公开(公告)日：2009-10-29

申请号：US12110589

申请日：2008-04-28

Applicant: Bixia Li ,  Hugh Mair ,  Minh Chau ,  Alice Wang ,  Uming Ko

Inventor： Bixia Li ,  Hugh Mair ,  Minh Chau ,  Alice Wang ,  Uming Ko

IPC: H03K19/003 ,  H03K3/02

CPC classification number: H03K3/0375

Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.

Abstract translation: 用于在电力域中异步降低功率的装置，系统和方法。 在一个实施例中，该方法包括：（1）接收功率域的睡眠命令，（2）在接收到睡眠命令时接收表示功率域中的保留区域已存储数据的肯定保持状态信号（ 3）在接收到睡眠命令时接收表示已经发生功率域隔离的肯定隔离状态信号，以及（4）至少在接收到睡眠命令时向功率域提供功率域关闭命令，肯定的 状态保持信号和肯定状态隔离信号。 在另一个实施例中，采用多个使能信号来产生功率开关的“无毛刺”控制。

公开(公告)号：US07519925B2

公开(公告)日：2009-04-14

申请号：US11139452

申请日：2005-05-27

Applicant: Sami Issa ,  Uming Ko ,  David Scott

Inventor： Sami Issa ,  Uming Ko ,  David Scott

IPC: G06F17/50

CPC classification number: G01R31/3004 ,  G06F17/5063

Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.

Abstract translation: 电子系统（10）。 该系统包括用于从电压源接收系统电压的电路（P1）。 系统还包括响应系统电压的用于提供数据处理功能的电路（141）。 用于提供数据处理功能的电路包括关键路径（CP1），并且关键路径包括多个晶体管。 多个晶体管中的至少一些晶体管具有对应于预测寿命的相应的预定电压工作极限。 该系统还包括用于指示关键路径的操作速度的潜在能力的电路（221）。 该系统还包括用于将系统电压耦合到关键路径的电路（CB）。 最后，该系统还包括用于响应于用于指示潜在能力的电路来调节由电压源提供的系统电压的电路（26）。 在选择的情况下，用于调整的电路将电压供应提供的电压调整为大于预定电压工作极限的电压，同时仍然符合预期的使用寿命。

公开(公告)号：US20080307240A1

公开(公告)日：2008-12-11

申请号：US11760263

申请日：2007-06-08

Applicant: Franck Dahan ,  Gilles Dubost ,  Gordon Gammie ,  Uming Ko ,  Hugh Mair ,  Sang-Won Song ,  Alice Wang ,  William D. Wilson

Inventor： Franck Dahan ,  Gilles Dubost ,  Gordon Gammie ,  Uming Ko ,  Hugh Mair ,  Sang-Won Song ,  Alice Wang ,  William D. Wilson

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/06 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F21/79 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172 ,  Y02D50/20

Abstract: An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).

Abstract translation: 一种电子电路，包括功率管理电路（2610）和耦合到功率管理电路（2610）的功率管理控制电路（3570），并且可操作以在至少第一操作性能点（OPP1）和第二较高操作 功率管理电路（2610）的性能点（OPP2），每个性能点包括电压和工作频率的相应对（Vn，Fn），并且功率管理控制电路（3570）还可操作以控制功率管理电路 功率管理电路（2610），其中在给定操作性能点处的功率管理电路（2610）具有静态功耗（4820.1），并且动态功率开关将功率管理电路置于较低的静态功率状态 4860.1），功耗比静态功耗（4820.1）要低。

公开(公告)号：US20070290270A1

公开(公告)日：2007-12-20

申请号：US11745250

申请日：2007-05-07

Applicant: Uming Ko ,  Dharin Shah ,  Senthil Sundaramoorthy ,  Girishankar Gurumurthy ,  Sumanth Gururajarao ,  Rolf Lagerquist ,  Clive Bittlestone

Inventor： Uming Ko ,  Dharin Shah ,  Senthil Sundaramoorthy ,  Girishankar Gurumurthy ,  Sumanth Gururajarao ,  Rolf Lagerquist ,  Clive Bittlestone

IPC: H01L29/768 ,  G06F17/50

CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/11807

Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

Abstract translation: 集成电路。 集成电路包括具有排列成行的布局的区域。 每行可由一对行边界定义。 集成电路还包括多个单元，包括第一组单元。 第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管 。

公开(公告)号：US07282905B2

公开(公告)日：2007-10-16

申请号：US11010135

申请日：2004-12-10

Applicant: Wei Chen ,  Hugh T. Mair ,  Uming Ko ,  David B. Scott

Inventor： Wei Chen ,  Hugh T. Mair ,  Uming Ko ,  David B. Scott

IPC: G01R31/26

CPC classification number: G01R31/3008 ,  G01R31/3012

Abstract: System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.

Abstract translation: 通过测量IDDQ来检测大型集成电路中的晶体管故障的系统和方法。 优选实施例包括由多个选择性地将电源子域耦合到电源引脚的多个主开关（例如主开关410）构成的集成电路的开关结构，多个pi开关（例如， 开关415）选择性地耦合功率子域对，以及选择性地将功率子域耦合到VIDDQ引脚的多个IDDQ开关（例如IDDQ开关425）。 pi开关可以对功率子域进行去耦，而IDDQ开关可以测量电源子域中的静态电流。 pi开关和IDDQ开关的使用可以允许测量电源子域中的静态电流，而不需要使用隔离缓冲器，并且需要在不同功率子域中的电流测量之间为集成电路供电和关断 。

公开(公告)号：US20070046362A1

公开(公告)日：2007-03-01

申请号：US11213477

申请日：2005-08-26

Applicant: Gordon Gammie ,  Alice Wang ,  Uming Ko ,  David Scott

Inventor： Gordon Gammie ,  Alice Wang ,  Uming Ko ,  David Scott

IPC: H03K3/01

CPC classification number: H03K19/0008 ,  H03K19/00384

Abstract: A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.

Abstract translation: 一种用于自适应地控制提供给设备附近的电路的电压的装置，包括耦合到处理模块的处理模块和第一跟踪元件。 第一跟踪元件产生指示与电路相关联的第一估计速度的第一值。 该装置还包括耦合到处理模块的第二跟踪元件。 第二跟踪元件产生指示与电路相关联的第二估计速度的第二值。 处理模块将第一和第二值中的每一个与各自的目标值进行比较，并且基于比较使得电压输出被调整。 第一和第二跟踪元件包括多个晶体管，至少一些晶体管选择性地提供晶体管偏置电压以调整晶体管速度。

公开(公告)号：US20060267654A1

公开(公告)日：2006-11-30

申请号：US11138788

申请日：2005-05-26

Applicant: Sumanth Gururajarao ,  Hugh Mair ,  David Scott ,  Uming Ko

Inventor： Sumanth Gururajarao ,  Hugh Mair ,  David Scott ,  Uming Ko

IPC: H03K3/356

CPC classification number: H03K3/356008 ,  H04W52/0283 ,  Y02D70/122

Abstract: In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

公开(公告)号：US20060033551A1

公开(公告)日：2006-02-16

申请号：US10918869

申请日：2004-08-16

Applicant: Wei Dong ,  Hiep Tran ,  Hugh Mair ,  Uming Ko

Inventor： Wei Dong ,  Hiep Tran ,  Hugh Mair ,  Uming Ko

IPC: H03K17/687

CPC classification number: H03K19/00346 ,  H03K17/166 ,  H03K17/167 ,  H03K17/687 ,  H03K19/0016

Abstract: System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

Abstract translation: 为电路提供电源同时避免大的瞬态电流的系统和方法。 优选实施例包括具有将电源耦合到电路的多个开关（例如开关405）的分布式开关（例如开关装置400）。 每个开关由控制信号单独控制，并依次打开。 还耦合到每个开关是预驱动器电路（例如预驱动器电路410）。 预驱动电路包括一个电位调节电路（例如电位调节电路505），其快速地调节开关处的电压电位;以及速率调节电路（例如速率调整电路520），其加速横跨 一旦瞬态电流不再需要切换， 调整电压电位以使开关工作在饱和模式，从而增加开关两端的有效电容，从而延迟开关上的功率上升。

公开(公告)号：US20050273742A1

公开(公告)日：2005-12-08

申请号：US11139452

申请日：2005-05-27

Applicant: Sami Issa ,  Uming Ko ,  David Scott

Inventor： Sami Issa ,  Uming Ko ,  David Scott

IPC: G06F9/45

CPC classification number: G01R31/3004 ,  G06F17/5063

Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.

Abstract translation: 电子系统（10）。 该系统包括用于从电压源接收系统电压的电路（P 1 SUB）。 该系统还包括响应于系统电压的用于提供数据处理功能的电路（14 1 1）。 用于提供数据处理功能的电路包括关键路径（CP <1> 1），并且关键路径包括多个晶体管。 多个晶体管中的至少一些晶体管具有对应于预测寿命的相应的预定电压工作极限。 该系统还包括用于指示关键路径的操作速度的潜在能力的电路（22I 1）。 该系统还包括用于将系统电压耦合到关键路径的电路（CB）。 最后，该系统还包括用于响应于用于指示潜在能力的电路来调节由电压源提供的系统电压的电路（26）。 在选择的情况下，用于调整的电路将电压供应提供的电压调整为大于预定电压工作极限的电压，同时仍然符合预期的使用寿命。

公开(公告)号：US6151262A

公开(公告)日：2000-11-21

申请号：US426960

申请日：1999-10-26

Applicant: Baher S. Haroun ,  Uming Ko

Inventor： Baher S. Haroun ,  Uming Ko

IPC: G11C7/16 ,  G11C7/22 ,  H04M1/73 ,  G11C7/00

CPC classification number: G11C7/16 ,  G11C7/22

Abstract: This invention concerns power consumption control of memory having a fully powered state and at least one lower power state. The invention changes the memory to the fully powered state upon receipt of a memory access request. This memory access request is serviced in the fully powered state. The memory is returned to a lower power state after expiration of a grace period following a last memory access request. This grace period can be measured by a predetermined time or a predetermined number of memory access requests or a combination of these factors. The predetermined time may be fixed in manufacture or programmable in operation via a control register or data stored in a predetermined set of address locations within the address space of the memory. This invention is useful in portable electronic devices such as wireless telephones.

Abstract translation: 本发明涉及具有完全供电状态和至少一个较低功率状态的存储器的功耗控制。 本发明在接收到存储器访问请求时将存储器改变为完全供电状态。 该存储器访问请求在完全供电状态下被服务。 在最后一次存储器访问请求之后的宽限期期满之后，存储器返回到较低功率状态。 可以通过预定时间或预定数量的存储器访问请求或这些因素的组合来测量该宽限期。 预定时间可以通过控制寄存器或存储在存储器的地址空间内的预定的一组地址位置中的数据在制造中固定或在操作中可编程。 本发明在诸如无线电话的便携式电子设备中是有用的。