公开(公告)号：US09153600B2

公开(公告)日：2015-10-06

申请号：US13618308

申请日：2012-09-14

Applicant: Hye Young Ryu ,  Hee Jun Byeon ,  Woo Geun Lee ,  Kap Soo Yoon ,  Yoon Ho Kim ,  Chun Won Byun

Inventor： Hye Young Ryu ,  Hee Jun Byeon ,  Woo Geun Lee ,  Kap Soo Yoon ,  Yoon Ho Kim ,  Chun Won Byun

IPC: G02F1/1343 ,  G02F1/1362 ,  H01L27/12

CPC classification number: H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板及其制造方法在由有机绝缘体形成的第二钝化层中形成接触孔，通过用由保护构件形成的保护构件覆盖来保护接触孔的一侧 与第一场产生电极相同的层并由透明导电材料形成，并且使用保护构件作为掩模，将第二钝化层下面的第一钝化层蚀刻。 因此，可以防止由有机绝缘体形成的第二钝化层在蚀刻第二钝化层下方的绝缘层的同时进行过蚀刻，从而防止接触孔过宽。

公开(公告)号：US08866137B2

公开(公告)日：2014-10-21

申请号：US13365704

申请日：2012-02-03

Applicant: Jin-Won Lee ,  Woo Geun Lee ,  Kap Soo Yoon ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Hee-Jun Byeon ,  Ji-Soo Oh

Inventor： Jin-Won Lee ,  Woo Geun Lee ,  Kap Soo Yoon ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Hee-Jun Byeon ,  Ji-Soo Oh

IPC: H01L29/12 ,  H01L27/12 ,  H01L29/417

CPC classification number: H01L27/1225 ,  H01L29/41733

Abstract: A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.

Abstract translation: 薄膜晶体管阵列面板包括：设置在绝缘基板上的栅电极; 设置在栅电极上的栅极绝缘层; 直接设置在栅极绝缘层上的第一电极和氧化物半导体; 形成在所述氧化物半导体上的源电极和漏电极; 设置在所述第一电极，所述源电极和所述漏电极上的钝化层; 以及设置在钝化层上的第二电极。

公开(公告)号：US08796675B2

公开(公告)日：2014-08-05

申请号：US13613566

申请日：2012-09-13

Applicant: Je-Hun Lee ,  Ki-Won Kim ,  Do-Hyun Kim ,  Woo-Geun Lee ,  Kap-Soo Yoon

Inventor： Je-Hun Lee ,  Ki-Won Kim ,  Do-Hyun Kim ,  Woo-Geun Lee ,  Kap-Soo Yoon

IPC: H01L35/24

CPC classification number: H01L27/1225 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Abstract translation: TFT阵列基板包括设置在绝缘基板上并包括沟道部分的半导体氧化物层，与半导体氧化物层重叠的栅极电极，插入在半导体氧化物层和栅电极之间的栅极绝缘层，以及设置在 半导体氧化物层和栅电极。 栅极绝缘层和钝化层中的至少一个包括氧氮化物层，并且氧氮化物层在氧氮化物层的位置更靠近半导体氧化物层的位置处具有比氮的浓度高的氧氮化物层。

公开(公告)号：US08735890B2

公开(公告)日：2014-05-27

申请号：US13328658

申请日：2011-12-16

Applicant: Ki-Won Kim ,  Je-Hun Lee ,  Sung-Haeng Cho ,  Woo-Geun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Seung-Ha Choi

Inventor： Ki-Won Kim ,  Je-Hun Lee ,  Sung-Haeng Cho ,  Woo-Geun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Seung-Ha Choi

IPC: H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1288

Abstract: In a display substrate and a method of manufacturing the display substrate, the display substrate includes a data line, a channel pattern, an insulating pattern and a pixel electrode. The data line extends in a direction on a base substrate. The channel pattern is disposed in a separate region between an input electrode connected to the data line and an output electrode spaced apart from the input electrode. The channel pattern makes contact with the input electrode and the output electrode on the input and output electrodes. The insulating pattern is spaced apart from the channel pattern on the base substrate and includes a contact hole exposing the output electrode. The pixel electrode is formed on the insulating pattern to make contact with the output electrode through the contact hole. Thus, a damage of the oxide semiconductor layer may be minimized and a manufacturing process may be simplified.

Abstract translation: 在显示基板和显示基板的制造方法中，显示基板包括数据线，通道图案，绝缘图案和像素电极。 数据线沿着基底基板上的方向延伸。 通道图案设置在与数据线连接的输入电极和与输入电极间隔开的输出电极之间的分离区域中。 通道图案与输入电极和输出电极上的输出电极接触。 绝缘图案与基底基板上的沟道图案间隔开，并且包括暴露输出电极的接触孔。 像素电极形成在绝缘图案上，以通过接触孔与输出电极接触。 因此，可以使氧化物半导体层的损伤最小化，并且可以简化制造工艺。

公开(公告)号：US08624238B2

公开(公告)日：2014-01-07

申请号：US13004665

申请日：2011-01-11

Applicant: Jong-In Kim ,  Young-Wook Lee ,  Jean-Ho Song ,  Jae-Hyoung Yoon ,  Sung-Ryul Kim ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Woo-Geun Lee

Inventor： Jong-In Kim ,  Young-Wook Lee ,  Jean-Ho Song ,  Jae-Hyoung Yoon ,  Sung-Ryul Kim ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Woo-Geun Lee

IPC: H01L21/34 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.

Abstract translation: 使用减少数量的掩模制造具有减少的缺陷的薄膜晶体管（TFT）基板。 TFT基板包括形成在基板上的栅极布线。 栅极布线包括栅电极。 在栅极布线上形成半导体图形。 在半导体图案上形成蚀刻停止图案。 数据布线包括形成在半导体图案上的源电极和蚀刻停止图案。 栅极布线和数据布线中的每一个包括在含铜层上形成的含铜层和缓冲层。

公开(公告)号：US20130214299A1

公开(公告)日：2013-08-22

申请号：US13618308

申请日：2012-09-14

Applicant: Hye Young RYU ,  Hee Jun BYEON ,  Woo Geun LEE ,  Kap Soo YOON ,  Yoon Ho KIM ,  Chun Won BYUN

Inventor： Hye Young RYU ,  Hee Jun BYEON ,  Woo Geun LEE ,  Kap Soo YOON ,  Yoon Ho KIM ,  Chun Won BYUN

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板及其制造方法在由有机绝缘体形成的第二钝化层中形成接触孔，通过用由保护构件形成的保护构件覆盖来保护接触孔的一侧 与第一场产生电极相同的层并由透明导电材料形成，并且使用保护构件作为掩模，将第二钝化层下面的第一钝化层蚀刻。 因此，可以防止由有机绝缘体形成的第二钝化层在蚀刻第二钝化层下方的绝缘层的同时进行过蚀刻，从而防止接触孔过宽。

公开(公告)号：US08389998B2

公开(公告)日：2013-03-05

申请号：US13444768

申请日：2012-04-11

Applicant: Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

Inventor： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC: H01L27/14

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

Abstract translation: 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US08313988B2

公开(公告)日：2012-11-20

申请号：US11646126

申请日：2006-12-27

Applicant: Sang-Woo Whangbo ,  Shi-Yul Kim ,  Sung-Hoon Yang ,  Woo-Geun Lee

Inventor： Sang-Woo Whangbo ,  Shi-Yul Kim ,  Sung-Hoon Yang ,  Woo-Geun Lee

IPC: H01L21/00 ,  H01L21/84

Abstract: A thin film transistor substrate includes a base substrate, a gate electrode, a gate insulating layer, a surface treating layer, an active layer, a source electrode and a drain electrode. The gate electrode is formed on the base substrate. The gate insulating layer is formed on the base substrate to cover the gate electrode. The surface treating layer is formed on the gate insulating layer by treating the gate insulating layer with a nitrogen-containing gas to prevent leakage current. The active layer is formed on the surface treating layer to cover the gate electrode. The source electrode and the gate electrode that are spaced apart from each other by a predetermined distance are formed on the active layer.

公开(公告)号：US20120217493A1

公开(公告)日：2012-08-30

申请号：US13365704

申请日：2012-02-03

Applicant: Jin-Won LEE ,  Woo Geun LEE ,  Kap Soo YOON ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Hee-Jun BYEON ,  Ji-Soo OH

Inventor： Jin-Won LEE ,  Woo Geun LEE ,  Kap Soo YOON ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Hee-Jun BYEON ,  Ji-Soo OH

IPC: H01L29/786 ,  H01L33/02 ,  H01L29/24

CPC classification number: H01L27/1225 ,  H01L29/41733

Abstract: A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.

Abstract translation: 薄膜晶体管阵列面板包括：设置在绝缘基板上的栅电极; 设置在栅电极上的栅极绝缘层; 直接设置在栅极绝缘层上的第一电极和氧化物半导体; 形成在所述氧化物半导体上的源电极和漏电极; 设置在所述第一电极，所述源电极和所述漏电极上的钝化层; 以及设置在钝化层上的第二电极。

公开(公告)号：US08216865B2

公开(公告)日：2012-07-10

申请号：US12772836

申请日：2010-05-03

Applicant: Young-Joo Choi ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Ki-Won Kim

Inventor： Young-Joo Choi ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Ki-Won Kim

IPC: H01L21/00

CPC classification number: H01L27/124 ,  C23F1/02 ,  C23F1/18 ,  C23F1/26 ,  H01L21/32134 ,  H01L21/465 ,  H01L27/1225

Abstract: A display device includes a gate pattern, a semiconductor pattern, a source pattern and a pixel electrode are provided. The gate pattern is formed on a base substrate and includes a gate line and a gate electrode. The semiconductor pattern is formed on the base substrate having the gate pattern and includes an oxide semiconductor. The source pattern is formed from a data metal layer and formed on the base substrate having the semiconductor pattern, and includes a data line, a source electrode and a drain electrode. The data metal layer includes a first copper alloy layer, and a lower surface of the data metal layer substantially coincides with an upper surface of the semiconductor pattern. The pixel electrode is formed on the base substrate having the source pattern and electrically connected to the drain electrode. Thus, manufacturing processes may be simplified, and reliability may be improved.

Abstract translation: 显示装置包括栅极图案，半导体图案，源图案和像素电极。 栅极图案形成在基底基板上，并且包括栅极线和栅电极。 半导体图案形成在具有栅极图案的基底基板上，并且包括氧化物半导体。 源图案由数据金属层形成并形成在具有半导体图案的基底基板上，并且包括数据线，源电极和漏电极。 数据金属层包括第一铜合金层，数据金属层的下表面基本上与半导体图案的上表面重合。 像素电极形成在具有源极图案的基底基板上并与漏电极电连接。 因此，可以简化制造工艺，并且可以提高可靠性。