公开(公告)号：US08216865B2

公开(公告)日：2012-07-10

申请号：US12772836

申请日：2010-05-03

申请人： Young-Joo Choi ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Ki-Won Kim

发明人： Young-Joo Choi ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Ki-Won Kim

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  C23F1/02 ,  C23F1/18 ,  C23F1/26 ,  H01L21/32134 ,  H01L21/465 ,  H01L27/1225

摘要： A display device includes a gate pattern, a semiconductor pattern, a source pattern and a pixel electrode are provided. The gate pattern is formed on a base substrate and includes a gate line and a gate electrode. The semiconductor pattern is formed on the base substrate having the gate pattern and includes an oxide semiconductor. The source pattern is formed from a data metal layer and formed on the base substrate having the semiconductor pattern, and includes a data line, a source electrode and a drain electrode. The data metal layer includes a first copper alloy layer, and a lower surface of the data metal layer substantially coincides with an upper surface of the semiconductor pattern. The pixel electrode is formed on the base substrate having the source pattern and electrically connected to the drain electrode. Thus, manufacturing processes may be simplified, and reliability may be improved.

摘要翻译： 显示装置包括栅极图案，半导体图案，源图案和像素电极。 栅极图案形成在基底基板上，并且包括栅极线和栅电极。 半导体图案形成在具有栅极图案的基底基板上，并且包括氧化物半导体。 源图案由数据金属层形成并形成在具有半导体图案的基底基板上，并且包括数据线，源电极和漏电极。 数据金属层包括第一铜合金层，数据金属层的下表面基本上与半导体图案的上表面重合。 像素电极形成在具有源极图案的基底基板上并与漏电极电连接。 因此，可以简化制造工艺，并且可以提高可靠性。

公开(公告)号：US20110079776A1

公开(公告)日：2011-04-07

申请号：US12772836

申请日：2010-05-03

申请人： Young-Joo Choi ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Ki-Won Kim

发明人： Young-Joo Choi ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Ki-Won Kim

IPC分类号： H01L33/26

CPC分类号： H01L27/124 ,  C23F1/02 ,  C23F1/18 ,  C23F1/26 ,  H01L21/32134 ,  H01L21/465 ,  H01L27/1225

摘要： A display device includes a gate pattern, a semiconductor pattern, a source pattern and a pixel electrode are provided. The gate pattern is formed on a base substrate and includes a gate line and a gate electrode. The semiconductor pattern is formed on the base substrate having the gate pattern and includes an oxide semiconductor. The source pattern is formed from a data metal layer and formed on the base substrate having the semiconductor pattern, and includes a data line, a source electrode and a drain electrode. The data metal layer includes a first copper alloy layer, and a lower surface of the data metal layer substantially coincides with an upper surface of the semiconductor pattern. The pixel electrode is formed on the base substrate having the source pattern and electrically connected to the drain electrode. Thus, manufacturing processes may be simplified, and reliability may be improved.

摘要翻译： 显示装置包括栅极图案，半导体图案，源图案和像素电极。 栅极图案形成在基底基板上，并且包括栅极线和栅电极。 半导体图案形成在具有栅极图案的基底基板上，并且包括氧化物半导体。 源图案由数据金属层形成并形成在具有半导体图案的基底基板上，并且包括数据线，源电极和漏电极。 数据金属层包括第一铜合金层，数据金属层的下表面基本上与半导体图案的上表面重合。 像素电极形成在具有源极图案的基底基板上并与漏电极电连接。 因此，可以简化制造工艺，并且可以提高可靠性。

公开(公告)号：US08723179B2

公开(公告)日：2014-05-13

申请号：US12957743

申请日：2010-12-01

申请人： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

发明人： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

摘要翻译： 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US08598577B2

公开(公告)日：2013-12-03

申请号：US13177783

申请日：2011-07-07

申请人： Jae-Woo Park ,  Dong-Hoon Lee ,  Sung-Haeng Cho ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Young-Joo Choi

发明人： Jae-Woo Park ,  Dong-Hoon Lee ,  Sung-Haeng Cho ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Young-Joo Choi

IPC分类号： H01L29/786

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/458

摘要： A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.

摘要翻译： 显示基板包括在基底基板上沿第一方向延伸的栅极线，在基底基板上的数据线，并且沿与第一方向交叉的第二方向延伸，栅极线上的栅极绝缘层，薄膜晶体管和 像素电极。 薄膜晶体管包括栅电极，电极连接栅极线，氧化物半导体图案以及氧化物半导体图案上的源电极和漏电极并彼此间隔开。 氧化物半导体图案包括包括氧化铟的第一半导体图案和包含无铟氧化物的第二半导体图案。 像素电极与漏电极电连接。

公开(公告)号：US08994023B2

公开(公告)日：2015-03-31

申请号：US13115088

申请日：2011-05-24

申请人： Hye-Young Ryu ,  Woo-Geun Lee ,  Young-Joo Choi ,  Kyoung-Jae Chung ,  Jin-Won Lee ,  Seung-Ha Choi ,  Hee-Jun Byeon ,  Pil-Sang Yun

发明人： Hye-Young Ryu ,  Woo-Geun Lee ,  Young-Joo Choi ,  Kyoung-Jae Chung ,  Jin-Won Lee ,  Seung-Ha Choi ,  Hee-Jun Byeon ,  Pil-Sang Yun

IPC分类号： H01L47/00 ,  H01L29/10 ,  H01L29/04 ,  H01L29/15 ,  H01L27/12

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/1255

摘要： A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

摘要翻译： 提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案 图案，以及形成在防蚀刻图案上的源电极和漏电极。 氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。

公开(公告)号：US20110284852A1

公开(公告)日：2011-11-24

申请号：US13049783

申请日：2011-03-16

申请人： Ki-Won KIM ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

发明人： Ki-Won KIM ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78645 ,  H01L29/78648

摘要： A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

摘要翻译： 薄膜晶体管包括半导体图案，第一栅电极，源电极，漏电极和第二栅电极。 半导体图案形成在基板上。 第一导电层具有包括与半导体图案电绝缘的第一栅电极的图案。 第二导电层具有图案，其包括电连接到半导体图案的源电极，与源电极间隔开的漏电极和与第一栅电极电连接的第二栅电极。 第二栅电极与半导体图案，源电极和漏电极电绝缘。

公开(公告)号：US08772897B2

公开(公告)日：2014-07-08

申请号：US13049783

申请日：2011-03-16

申请人： Ki-Won Kim ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

发明人： Ki-Won Kim ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

IPC分类号： H01L27/146

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78645 ,  H01L29/78648

摘要： A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

摘要翻译： 薄膜晶体管包括半导体图案，第一栅电极，源电极，漏电极和第二栅电极。 半导体图案形成在基板上。 第一导电层具有包括与半导体图案电绝缘的第一栅电极的图案。 第二导电层具有图案，其包括电连接到半导体图案的源电极，与源电极间隔开的漏电极和与第一栅电极电连接的第二栅电极。 第二栅电极与半导体图案，源电极和漏电极电绝缘。

公开(公告)号：US20080203393A1

公开(公告)日：2008-08-28

申请号：US12099718

申请日：2008-04-08

申请人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L27/088

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US08173493B2

公开(公告)日：2012-05-08

申请号：US12765698

申请日：2010-04-22

申请人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US07425476B2

公开(公告)日：2008-09-16

申请号：US11242696

申请日：2005-10-04

申请人： Woo-Geun Lee ,  Hye-Young Ryu ,  Sang-Gab Kim ,  Jang-Soo Kim

发明人： Woo-Geun Lee ,  Hye-Young Ryu ,  Sang-Gab Kim ,  Jang-Soo Kim

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/1214 ,  H01L29/66765

摘要： A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a source electrode and a drain electrode on the ohmic contacts, depositing a passivation layer on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode. The formation of the data line and the drain electrode, the ohmic contacts, and the semiconductor stripe includes depositing an intrinsic silicon layer, an extrinsic silicon layer, and a conductor layer on the gate insulating layer, forming a photoresist including a second portion corresponding to a channel area between the source electrode and the drain electrode, and a first portion corresponding to a wire area on the data line and the drain electrode, wherein the first portion is thicker than the second portion, etching the conductor layer corresponding to a remaining area except for the wire and the channel area using the photoresist as an etch mask, removing the second portion to expose the conductor layer on the channel areas, etching the intrinsic silicon layer and the extrinsic silicon layer on the remaining area, etching the conductor layer and the extrinsic silicon layer on the channel areas, and removing the first portion.

摘要翻译： 制造薄膜晶体管阵列面板的方法包括：形成包括栅电极的栅极线，在栅极线上形成栅绝缘层，在栅绝缘层上形成半导体条; 在半导体条上形成欧姆接触，在欧姆接触上形成包括源电极和漏电极的数据线，在数据线和漏电极上沉积钝化层，并形成连接到漏电极的像素电极。 数据线和漏电极，欧姆接触和半导体条纹的形成包括在栅绝缘层上沉积本征硅层，非本征硅层和导体层，形成光致抗蚀剂，其包括对应于 源极电极和漏极电极之间的沟道区域，以及对应于数据线和漏极电极的导线区域的第一部分，其中第一部分比第二部分厚，蚀刻对应于剩余区域的导体层 除了使用光致抗蚀剂作为蚀刻掩模的导线和沟道区域之外，去除第二部分以暴露沟道区域上的导体层，蚀刻剩余区域上的本征硅层和非本征硅层，蚀刻导体层和 在通道区域上的非本征硅层，以及去除第一部分。