公开(公告)号：US5942780A

公开(公告)日：1999-08-24

申请号：US689523

申请日：1996-08-09

Applicant: Radu M. Barsan ,  Xiao-Yu Li ,  Sunil Mehta

Inventor： Radu M. Barsan ,  Xiao-Yu Li ,  Sunil Mehta

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558

Abstract: An integrated circuit ("IC") having three different oxide layer thicknesses and a process for manufacturing the IC using a single oxide growth step is provided. A first region is formed on a substrate surface with oxidation enhancing properties. A second region is formed on the substrate surface with a dose of nitrogen that retards oxidation. An oxide layer is grown from the first and the second regions and a third region of the substrate such that the first, second, and third regions yield a first oxide layer for the capacitor, a second oxide layer for the read transistor and a third oxide layer for the write transistor.

Abstract translation: 提供具有三种不同氧化物层厚度的集成电路（“IC”）和使用单一氧化物生长步骤制造该IC的工艺。 第一区域形成在具有氧化增强性质的基板表面上。 在衬底表面上形成一个第二区域，其中氮气的量减少了氧化。 从基板的第一和第二区域和第三区域生长氧化物层，使得第一，第二和第三区域产生用于电容器的第一氧化物层，用于读取晶体管的第二氧化物层和第三氧化物层 写入晶体管层。

公开(公告)号：US09161178B2

公开(公告)日：2015-10-13

申请号：US14009008

申请日：2011-03-30

Applicant: Liang Chen ,  Xiao-Yu Li ,  Jason Xu

Inventor： Liang Chen ,  Xiao-Yu Li ,  Jason Xu

IPC: H04W4/00 ,  H04W4/06 ,  H04W4/08

CPC classification number: H04W4/06 ,  H04W4/08

Abstract: Methods and apparatus are provided for communicating a message to multiple radio groups (102, 104). An exemplary method (300) involves configuring, by an initiating radio device (120), a header portion of a message (308) for a multi-group communication session including the plurality of radio groups (102, 104) and transmitting the message (310). Each respective radio device (110) of each respective radio group (102, 104) is configured to provide output (408) corresponding to a content portion of the message in response to identifying its own radio group (406) in the header portion of the message (404).

Abstract translation: 提供了用于将消息传送到多个无线电组（102,104）的方法和装置。 示例性方法（300）涉及通过发起无线电设备（120）配置用于包括多个无线电组（102,104）的多组通信会话的消息（308）的报头部分，并发送消息（ 310）。 每个相应无线电组（102,104）的每个相应无线电设备（110）被配置为响应于在其中的标题部分中识别其自己的无线电组（406）来提供与消息的内容部分相对应的输出（408） 消息（404）。

公开(公告)号：US07020860B1

公开(公告)日：2006-03-28

申请号：US10808737

申请日：2004-03-24

Applicant: Joe W. Zhao ,  Xiao-Yu Li ,  Feng Wang ,  Zhi-Min Ling

Inventor： Joe W. Zhao ,  Xiao-Yu Li ,  Feng Wang ,  Zhi-Min Ling

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G01R31/318321 ,  G01R31/318519

Abstract: Methods for monitoring and improving the fabrication process of integrated circuits using configurable devices are described. In one aspect, the method includes instantiating a test pattern on one or more configurable devices fabricated using the fabrication process, identifying an underperforming region of the configurable devices, and determining if the underperforming region is layout sensitive. At least one of the fabrication process and the layout of the configurable device can then be adjusted based on the determination. In some embodiments, the configurable device may be a programmable logic device, such as a field programmable logic array.

Abstract translation: 描述了使用可配置的装置来监测和改进集成电路的制造过程的方法。 在一个方面，该方法包括在使用制造工艺制造的一个或多个可配置的设备上实例化测试图案，识别可配置设备的表现不佳的区域，以及确定表现不佳的区域是否是布局敏感的。 然后可以基于确定来调整可配置设备的制造过程和布局中的至少一个。 在一些实施例中，可配置设备可以是可编程逻辑设备，诸如现场可编程逻辑阵列。

公开(公告)号：US06404006B2

公开(公告)日：2002-06-11

申请号：US09203149

申请日：1998-12-01

Applicant: Xiao-Yu Li ,  Steven J. Fong

Inventor： Xiao-Yu Li ,  Steven J. Fong

IPC: H01L29788

CPC classification number: H01L27/11521 ,  G11C16/0441 ,  H01L27/115 ,  H01L27/11558

Abstract: An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (PMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer having a thickness to allow the electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the tunnel channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer having a thickness to allow electron tunneling across an entire portion of a tunneling channel upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.

Abstract translation: 描述了通过遍及分离的晶体管通道的整个部分的电子隧道编程和擦除的EEPROM单元。 EEPROM单元具有形成在半导体衬底中的三个晶体管。 三个晶体管是隧道晶体管（PMOS），感测晶体管（NMOS）和读取晶体管（NMOS）。 发生电子隧穿，以通过具有厚度的感测隧道氧化物层对EEPROM单元进行编程，以便在浮动栅极和隧道通道之间发生足够的电压电势时允许跨越感测通道的整个部分的电子隧穿。 还发生电子隧穿，以通过具有厚度的隧道氧化物层擦除EEPROM电池，以在浮动栅极和隧道通道之间发生足够的电压电势时允许穿过隧道通道的整个部分的电子隧穿。

公开(公告)号：US06309942B1

公开(公告)日：2001-10-30

申请号：US09245161

申请日：1999-02-04

Applicant: Ting Y. Tsui ,  Robert H. Tu ,  Xiao-Yu Li ,  Sunil D. Mehta

Inventor： Ting Y. Tsui ,  Robert H. Tu ,  Xiao-Yu Li ,  Sunil D. Mehta

IPC: H01L2176

CPC classification number: H01L21/76229

Abstract: A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.

Abstract translation: 公开了一种制造具有减小的浅沟槽隔离缺陷和应力的半导体器件的方法。 所公开的方法开始于提供包括封盖层的硅衬底。 然后通过覆盖层蚀刻多个隔离沟槽并进入硅衬底，以在硅衬底中形成多个隔离区域。 然后用氧化物层填充隔离沟槽。 然后使用本领域已知的技术将氧化物层和覆盖层进行抛光。 在抛光之后，半导体器件在约1150℃至约1200℃的温度范围内退火

公开(公告)号：US06294811B1

公开(公告)日：2001-09-25

申请号：US09245813

申请日：1999-02-05

Applicant: Steven J. Fong ,  Xiao-Yu Li

Inventor： Steven J. Fong ,  Xiao-Yu Li

IPC: H01L29788

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/7883

Abstract: A two transistor EEPROM cell is described that is erased by electron tunneling across an entire portion of a tunneling channel and programmed by electron tunneling at an edge of a tunneling drain.

Abstract translation: 描述了两个晶体管EEPROM单元，其通过穿过隧道通道的整个部分的电子隧穿而被擦除，并且通过在隧道漏极的边缘处的电子隧道编程。

公开(公告)号：US06261944B1

公开(公告)日：2001-07-17

申请号：US09200395

申请日：1998-11-24

Applicant: Sunil D. Mehta ,  Xiao-Yu Li

Inventor： Sunil D. Mehta ,  Xiao-Yu Li

IPC: H01L214763

CPC classification number: H01L21/316 ,  H01L21/76819 ,  H01L21/76825 ,  H01L23/3192 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization layer expose bonding pads in the multi-level interconnect layer. In a process for fabricating the device, the planarization layer is preferably formed by dispensing a siloxane spin-on-glass (SOG) material onto the surface of the multi-level interconnect layer. The SOG is subsequently planarized to form a substantially planar surface.

Abstract translation: 具有高可靠性钝化的半导体器件包括覆盖多层互连层的平坦化层。 钝化层具有平坦表面，在其上形成附加的钝化层。 上覆钝化层和平坦化层中的开口暴露多层互连层中的焊盘。 在制造该器件的过程中，平坦化层优选通过将硅氧烷旋涂玻璃（SOG）材料分配到多层互连层的表面上而形成。 SOG随后被平坦化以形成基本平坦的表面。

公开(公告)号：US5795627A

公开(公告)日：1998-08-18

申请号：US799236

申请日：1997-02-14

Applicant: Sunil Mehta ,  Emi Ishida ,  Xiao-Yu Li

Inventor： Sunil Mehta ,  Emi Ishida ,  Xiao-Yu Li

IPC: H01L21/316 ,  H01L21/762 ,  H01L27/115 ,  C23C14/04

CPC classification number: H01L21/76213 ,  H01L21/316 ,  H01L27/115

Abstract: A method of forming an oxide enhancing region, such as phosphorus, in a semiconductor substrate with minimal damage is provided. The method includes the steps of forming an oxide enhancing region in the semiconductor substrate to a depth below the semiconductor substrate. A 308 nm excimer laser is then applied to the oxide enhancing region in order to reduce the damage caused by forming the oxide enhancing region. A uniform and reliable oxide layer is then formed on the surface of the substrate over the damage reduced oxide enhancing region.

Abstract translation: 提供了在具有最小损伤的半导体衬底中形成诸如磷的氧化物增强区域的方法。 该方法包括以下步骤：在半导体衬底中形成半导体衬底下方的深度的氧化物增强区。 然后将308nm准分子激光器施加到氧化物增强区域，以便减少由形成氧化物增强区域引起的损伤。 然后在损伤还原氧化物增强区域上的衬底的表面上形成均匀且可靠的氧化物层。

公开(公告)号：US5761116A

公开(公告)日：1998-06-02

申请号：US726512

申请日：1996-10-07

Applicant: Xiao-Yu Li ,  Radu Barsan

Inventor： Xiao-Yu Li ,  Radu Barsan

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/115 ,  G11C16/0441

Abstract: An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines controlling the write and read transistors, respectively. With such a structure, lower voltages are used to program/erase the memory cell. The memory cell is scalable to small dimensions through the use of transistors having half-height tunnel oxide regions.

Abstract translation: 提供了具有多个半高隧道氧化物耗尽型晶体管的结构的增强型可扩展EEPROM存储单元。 该结构还分别具有控制写和晶体管的单个字线。 通过这样的结构，使用较低的电压来对存储单元进行编程/擦除。 通过使用具有半高隧道氧化物区域的晶体管，存储单元可缩放到小尺寸。

公开(公告)号：US5672521A

公开(公告)日：1997-09-30

申请号：US561306

申请日：1995-11-21

Applicant: Radu M. Barsan ,  Xiao-Yu Li ,  Sunil Mehta

Inventor： Radu M. Barsan ,  Xiao-Yu Li ,  Sunil Mehta

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/266

CPC classification number: H01L21/28185 ,  H01L21/2822 ,  H01L21/823462 ,  H01L29/518 ,  H01L21/28211 ,  Y10S148/116 ,  Y10S148/163 ,  Y10S438/981

Abstract: An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.

Abstract translation: 一种集成电路器件和制造方法，其中第一区域形成在具有增强氧化物形成的掺杂剂的衬底中，并且在衬底中形成具有延迟氧化物形成的氮的剂量的第二区域。 在衬底的第一和第二区域和第三区域上生长氧化物层，使得第一，第二和第三区域产生不同厚度的氧化物层。