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    Methods of fabricating vertical semiconductor device utilizing phase changes in semiconductor materials
    41.
    发明授权
    Methods of fabricating vertical semiconductor device utilizing phase changes in semiconductor materials 有权
    使用半导体材料相变的垂直半导体器件的制造方法

    公开(公告)号：US08236673B2

    公开(公告)日：2012-08-07

    申请号：US13024924

    申请日：2011-02-10

    申请人： Yong-hoon Son ,  Jin-ha Jeong ,  Jung-ho Kim ,  Vladimir Urazaev ,  Jong-hyuk Kang ,  Sung-woo Hyun

    发明人： Yong-hoon Son ,  Jin-ha Jeong ,  Jung-ho Kim ,  Vladimir Urazaev ,  Jong-hyuk Kang ,  Sung-woo Hyun

    IPC分类号： H01L21/20

    CPC分类号： H01L21/20

    摘要： A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening.

    摘要翻译： 制造垂直NAND半导体器件的方法可以包括将开口中的第一初级半导体层的相位从固体改变为在开口中形成第一单晶半导体层，然后在第一单个晶体管上形成第二初步半导体层 晶体半导体层。 第二初步半导体层的相位从固体变为液态，形成与第一单晶半导体层结合以在开口中形成单晶半导体层的第二单晶半导体层。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF FABRICATING THE SAME
    42.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF FABRICATING THE SAME 有权
    半导体集成电路装置及其制造方法

    公开(公告)号：US20120097950A1

    公开(公告)日：2012-04-26

    申请号：US13343967

    申请日：2012-01-05

    申请人： Yong-hoon SON ,  Si-young Choi ,  Jong-wook Lee

    发明人： Yong-hoon SON ,  Si-young Choi ,  Jong-wook Lee

    IPC分类号： H01L29/786 ,  H01L21/28

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

    摘要翻译： 一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层， 的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个 将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成 与单晶活性图案接触的栅电极。

    METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICE
    44.
    发明申请
    METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICE 有权
    制造垂直半导体器件的方法

    公开(公告)号：US20120088343A1

    公开(公告)日：2012-04-12

    申请号：US13325189

    申请日：2011-12-14

    申请人： Yong-Hoon SON ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon SON ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10852 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

    摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

    摘要翻译： 垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分， 所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层， 所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

    SEMICONDUCTOR DEVICES
    45.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开
    半导体器件

    公开(公告)号：US20120032250A1

    公开(公告)日：2012-02-09

    申请号：US13182269

    申请日：2011-07-13

    申请人： Yong-Hoon SON ,  Sung-Min HWANG ,  Kihyun HWANG ,  Jaehoon JANG

    发明人： Yong-Hoon SON ,  Sung-Min HWANG ,  Kihyun HWANG ,  Jaehoon JANG

    IPC分类号： H01L29/792

    CPC分类号： H01L21/76254 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42348

    摘要： A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate through the conductive patterns to provide vertical string transistors on the first substrate. A second substrate can be on the conductive patterns and the active pillar opposite the first substrate. A peripheral circuit transistor can be on the second substrate opposite the first substrate, where the peripheral circuit transistor can be adjacent to and overlap an uppermost pattern of the conductive patterns.

    摘要翻译： 半导体器件可以包括第一衬底和第一衬底上的导电图案，其中导电图案布置在从衬底垂直延伸的堆叠中。 活性柱可以在第一衬底上，从第一衬底经由导电图案垂直延伸，以在第一衬底上提供垂直串晶体管。 第二基板可以位于与第一基板相对的导电图案和有源柱上。 外围电路晶体管可以在与第一衬底相对的第二衬底上，其中外围电路晶体管可以与导电图案的最上面的图案相邻并且与其重叠。

    Semiconductor Memory Devices And Methods Of Forming The Same
    47.
    发明申请
    Semiconductor Memory Devices And Methods Of Forming The Same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US20110316064A1

    公开(公告)日：2011-12-29

    申请号：US13167858

    申请日：2011-06-24

    申请人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    发明人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    摘要： Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.

    摘要翻译： 可以提供半导体器件及其形成方法。 半导体器件可以包括在衬底上重复并交替堆叠的栅极图案和绝缘图案。 半导体器件还可以包括穿透栅极图案和绝缘图案的穿透区域。 半导体器件还可以包括从衬底延伸穿过区域的沟道结构。 通道结构可以包括具有第一形状的第一通道图案。 第一沟道图案可以包括贯通区域的一部分的侧壁上的第一半导体区域和分割第一半导体区域的掩埋图案。 通道结构还可以包括具有第二形状的第二通道图案。 第二沟道图案可以包括通孔区域中的第二半导体区域。 第二半导体区域的晶粒尺寸可以大于第一半导体区域的晶粒尺寸。

    Vertical type semiconductor device
    48.
    发明授权
    Vertical type semiconductor device 有权
    垂直型半导体器件

    公开(公告)号：US08063441B2

    公开(公告)日：2011-11-22

    申请号：US12588948

    申请日：2009-11-03

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/7827 ,  H01L29/66666

    摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

    摘要翻译： 垂直柱半导体器件可以包括衬底，沟道图案组，栅极绝缘层图案和栅电极。 衬底可分为有源区和隔离层。 可以在对应于有源区的衬底中形成第一杂质区。 通道图案组可以从有源区域的表面突出并且可以彼此平行地布置。 第二杂质区可以形成在沟道图案组的上部。 栅极绝缘层图案可以形成在衬底和沟道图案组的侧壁上。 栅极绝缘层图案可以与沟道图案组的上表面间隔开。 栅电极可以接触栅极绝缘层并且可以包围沟道图案组的侧壁。

    METHODS OF FABRICATING VERTICAL SEMICONDUCTOR DEVICE UTILIZING PHASE CHANGES IN SEMICONDUCTOR MATERIALS
    49.
    发明申请
    METHODS OF FABRICATING VERTICAL SEMICONDUCTOR DEVICE UTILIZING PHASE CHANGES IN SEMICONDUCTOR MATERIALS 有权
    在半导体材料中利用相变的垂直半导体器件制造方法

    公开(公告)号：US20110217828A1

    公开(公告)日：2011-09-08

    申请号：US13024924

    申请日：2011-02-10

    申请人： Yong-hoon Son ,  Jin-ha Jeong ,  Jung-ho Kim ,  Vladimir Urazaev ,  Jong-hyuk Kang ,  Sung-woo Hyun

    发明人： Yong-hoon Son ,  Jin-ha Jeong ,  Jung-ho Kim ,  Vladimir Urazaev ,  Jong-hyuk Kang ,  Sung-woo Hyun

    IPC分类号： H01L21/20

    CPC分类号： H01L21/20

    摘要： A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening.

    摘要翻译： 制造垂直NAND半导体器件的方法可以包括将开口中的第一初级半导体层的相位从固体改变为在开口中形成第一单晶半导体层，然后在第一单个晶体管上形成第二初步半导体层 晶体半导体层。 第二初步半导体层的相位从固体变为液态，形成与第一单晶半导体层结合以在开口中形成单晶半导体层的第二单晶半导体层。

    Vertical type semiconductor device, method of manufacturing a vertical type semiconductor device and method of operating a vertical semiconductor device
    50.
    发明申请
    Vertical type semiconductor device, method of manufacturing a vertical type semiconductor device and method of operating a vertical semiconductor device 审中-公开
    垂直型半导体器件，制造垂直型半导体器件的方法和操作垂直半导体器件的方法

    公开(公告)号：US20110205816A1

    公开(公告)日：2011-08-25

    申请号：US13064962

    申请日：2011-04-28

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L21/336 ,  G11C7/00

    CPC分类号： H01L27/11578 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

    摘要： A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.

    摘要翻译： 垂直柱半导体器件包括衬底，单晶半导体图案，栅极绝缘层结构和栅电极。 衬底可以包括第一杂质区域。 单晶半导体图案可以在第一杂质区上。 单晶半导体图案具有基本上垂直于基板的柱形。 可以在单晶半导体图案的上部形成第二杂质区。 栅极绝缘层结构可以包括电荷存储图案，单晶半导体图案的侧壁上的栅极绝缘层结构。 栅电极可以形成在栅极绝缘层结构上并且与单晶半导体图案的侧壁相对。 栅电极具有比单晶半导体图案基本上低的上表面。