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    SYSTEM-WIDE LOW POWER MANAGEMENT
    46.
    发明申请
    SYSTEM-WIDE LOW POWER MANAGEMENT 审中-公开

    公开(公告)号：US20190204899A1

    公开(公告)日：2019-07-04

    申请号：US15856546

    申请日：2017-12-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Greggory D. Donley ,  Bryan P. Broussard

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/5094

    Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

    Dynamic clock control to increase stutter efficiency in the memory subsystem
    48.
    发明授权
    Dynamic clock control to increase stutter efficiency in the memory subsystem 有权

    公开(公告)号：US10304506B1

    公开(公告)日：2019-05-28

    申请号：US15809608

    申请日：2017-11-10

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Alexander J. Branover ,  Benjamin Tsien ,  Bradley Kent ,  Joyce C. Wong

    IPC: H03L7/06 ,  G11C7/22 ,  G06F13/16 ,  G11C7/20

    Abstract: Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.

    SYSTEM AND METHOD FOR SECURITY PROCESSOR CONTROL OVER CPU POWER STATES
    50.
    发明申请
    SYSTEM AND METHOD FOR SECURITY PROCESSOR CONTROL OVER CPU POWER STATES 有权
    用于CPU功率状态下的安全处理器控制的系统和方法

    公开(公告)号：US20150121520A1

    公开(公告)日：2015-04-30

    申请号：US14529278

    申请日：2014-10-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Denis Rystsov ,  Sebastien Nussbaum

    IPC: G06F21/57 ,  G06F1/26 ,  G06F21/50

    CPC classification number: G06F21/57 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/50 ,  G06F21/81 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/171

    Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.

    Abstract translation: 本公开提供了用于控制处理器的一个或多个处理核心的功率状态（其可以包括C状态）的方法和装置。 在一方面，提出了一种确保处理器的电源状态改变的示例性方法，所述方法包括以下步骤：从处理器接收电力状态改变请求，所述处理器具有多个潜在功率状态，每个包括工作功率分布 ; 确定与所述处理器相关联的功率状态改变请求模式; 将所述电力状态改变请求转发到所述电力状态改变请求模式是一次性请求模式的安全处理器; 响应于该请求从安全处理器接收电力状态改变请求响应; 以及将所述处理器的当前功率状态调整到所述电力状态改变请求响应包括电力状态改变许可的所述目标电力状态。

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