公开(公告)号：US07340552B2

公开(公告)日：2008-03-04

申请号：US11642511

申请日：2006-12-21

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US5881255A

公开(公告)日：1999-03-09

申请号：US847974

申请日：1997-04-21

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/368 ,  G06F13/40 ,  G06F12/00

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

公开(公告)号：US5737589A

公开(公告)日：1998-04-07

申请号：US308346

申请日：1994-09-19

申请人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

发明人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

IPC分类号： G06F13/42 ,  G06F1/12 ,  H04J3/06 ,  H04L7/02 ,  G06F1/06

CPC分类号： H04L7/02

摘要： The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

摘要翻译： 通过根据通过检测采样偏差确定的误差信号的反馈来控制接收机采样时钟和主时钟之间的相位差，相对于用于发起发送的主时钟，连续地调整接收机处的数字信号采样定时 在启动操作和正常操作期间，从期望的基准定时的时钟定时。 通过将采样时钟设置在启动时的所需参考时序来补偿各个器件中的传播延迟散射。 通过在正常工作期间根据接收到的数字信号检测采样时钟定时与参考定时的偏差，然后根据检测结果连续校正采样时钟定时来补偿在器件工作期间引起的传播延迟散射。

公开(公告)号：US5678062A

公开(公告)日：1997-10-14

申请号：US199889

申请日：1994-02-22

申请人： Tetsuhiko Okada ,  Hideki Murayama ,  Takehisa Hayashi ,  Atsushi Ugajin ,  Yasuhiro Ishii ,  Masahiro Kitano

发明人： Tetsuhiko Okada ,  Hideki Murayama ,  Takehisa Hayashi ,  Atsushi Ugajin ,  Yasuhiro Ishii ,  Masahiro Kitano

IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： A system for controlling the DMA transfer for a plurality of IO devices has an IO controller for each group of the IO devices. Data is retrieved from memory and stored in the IO controller where it is analyzed. The retrieved data has a structure that permits a group of DMA start request quads to be linked together for parallel or pipeline processing of the DMA transfer requests. Each start request quad has a pointer for additionally retrieving corresponding command data. The command data is set forth in a number of blocks, each linked to the next one by a pointer. When a DMA processing has been completed, the termination or completion status is entered into a specific entry in a completion list for the corresponding IO device. Thus, a determination can be made as to whether specific IO devices have completed a requested DMA processing. Expansion of the system is accomplished by using combinations of main and sub controllers, where one main controller provides the aforementioned data structures for many sub controllers in order to enable the DMA processing to be performed for IO devices connected to the sub controllers with less frequent access of system main memory and the system bus.

摘要翻译： 用于控制多个IO设备的DMA传输的系统具有用于每组IO设备的IO控制器。 数据从存储器检索并存储在IO控制器中进行分析。 检索的数据具有允许一组DMA启动请求四元组链接在一起以用于DMA传送请求的并行或流水线处理的结构。 每个启动请求四元组都有一个指针，用于附加地检索相应的命令数据。 命令数据在多个块中设置，每个块通过指针链接到下一个块。 当DMA处理完成时，终止或完成状态将被输入到对应的IO设备的完成列表中的特定条目中。 因此，可以确定特定的IO设备是否已经完成了所请求的DMA处理。 通过使用主控制器和副控制器的组合来实现系统的扩展，其中一个主控制器为许多子控制器提供上述数据结构，以便能够对连接到具有较少频率访问的子控制器的IO设备执行DMA处理 的系统主存和系统总线。

公开(公告)号：US5671371A

公开(公告)日：1997-09-23

申请号：US544727

申请日：1995-10-18

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/368 ,  G06F13/40 ,  G06I13/00

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US5649102A

公开(公告)日：1997-07-15

申请号：US348099

申请日：1994-11-25

申请人： Masahiko Yamauchi ,  Satoshi Yoshizawa ,  Hideki Murayama ,  Takehisa Hayashi ,  Akira Kito ,  Hiroshi Yashiro ,  Tsutomu Goto ,  Kimitoshi Yamada ,  Toru Horimoto

发明人： Masahiko Yamauchi ,  Satoshi Yoshizawa ,  Hideki Murayama ,  Takehisa Hayashi ,  Akira Kito ,  Hiroshi Yashiro ,  Tsutomu Goto ,  Kimitoshi Yamada ,  Toru Horimoto

IPC分类号： G06F9/46 ,  G06F15/16

CPC分类号： G06F9/52

摘要： A distributed shared memory management system for a distributed shared memory computer system having a plurality of computers interconnected by a network, each computer having an independent address space and logically sharing data physically distributed to a storage of each computer. Each computer running a program for reading/changing the shared data includes a coherence control designation command for designating to enter a mutual exclusion state in which two or more computers cannot change the logically single shared data, a coherence control release command for designating a release of the mutual exclusion state, and a coherence control execution command for reflecting the contents of the shared data changed between the coherence control designation command and the coherence control release command, upon the logically single shared data in another computer. At least one of the plurality of computers includes a request message queue for storing a coherence control request message issued by the coherence control execution command when the coherence control designation command is executed. The coherence control designation command includes data for designating the order of reading/changing the shared data, and the request message queue includes a counter for storing a current state regarding the control of the order of reading/changing the shared data and a unit for storing a value regarding the control of the order of reading/changing the shared data.

摘要翻译： 一种用于分布式共享存储器计算机系统的分布式共享存储器管理系统，其具有通过网络互连的多个计算机，每个计算机具有独立的地址空间，并且逻辑上共享数据，物理分布到每个计算机的存储器。 运行用于读取/更改共享数据的程序的每个计算机包括用于指定进入两个或多个计算机不能改变逻辑上单个共享数据的互斥状态的相干控制指定命令，用于指定释放的相干控制释放命令 相互排除状态，以及用于反映在相干控制指定命令和相干控制释放命令之间改变的共享数据的内容的相干控制执行命令，在另一计算机中的逻辑单个共享数据上。 当执行相干控制指定命令时，多个计算机中的至少一个包括用于存储由相干控制执行命令发出的相干控制请求消息的请求消息队列。 相干控制指定命令包括用于指定读取/改变共享数据的顺序的数据，并且请求消息队列包括用于存储关于读取/改变共享数据的顺序的控制的当前状态的计数器和用于存储的单元 关于控制读取/改变共享数据的顺序的值。

公开(公告)号：US5517619A

公开(公告)日：1996-05-14

申请号：US203265

申请日：1994-02-28

申请人： Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Takehisa Hayashi ,  Teruo Tanaka ,  Shigeo Nagashima

发明人： Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Takehisa Hayashi ,  Teruo Tanaka ,  Shigeo Nagashima

IPC分类号： G06F13/40 ,  G06F15/173 ,  G06F13/38

CPC分类号： G06F15/17375 ,  G06F13/4022 ,  G06F15/17381

摘要： In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates (i.sub.1, i.sub.2, - - - , i.sub.k-1, i.sub.k+1, - - - , i.sub.N) of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).

摘要翻译： 在包括L = n1xn2x - - - xnN处理器元件或以外的设备（以下由处理器元件表示）的并行计算机中，使用Lx（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关的处理器元件的互连网络 总共包括N维网格坐标（i1，i2，...，iN），0

公开(公告)号：US5497488A

公开(公告)日：1996-03-05

申请号：US402560

申请日：1995-03-13

申请人： Mitsuru Akizawa ,  Kouki Noguchi ,  Takehisa Hayashi ,  Kanji Kato ,  Hitoshi Matsushima

发明人： Mitsuru Akizawa ,  Kouki Noguchi ,  Takehisa Hayashi ,  Kanji Kato ,  Hitoshi Matsushima

IPC分类号： G06F7/02 ,  G06F17/30

CPC分类号： G06F17/30979 ,  G06F17/30982 ,  G06F17/30985 ,  G06F7/02 ,  G06F2207/025 ,  Y10S707/99936

摘要： A character string search arithmetic operation is performed at high speed with a small hardware scale processing module, such as a symbol string search module. The search module is connected to a CPU through address and data buses and includes a function definition section for defining a function of the apparatus in accordance with a command from the CPU, a data input/output section for receiving a symbol string to be searched through the data bus and for outputting the result of a search. A search processing section performs the search based on a function defined by the function definition section. A symbol string to be searched for, which is internally stored, is compared with the symbol string data input to the module's data input/output means. A condition holding section holds data indicative of an internal condition corresponding to the result of the search processing. Thereby, the CPU and the symbol string search module can perform the search at high speed.

摘要翻译： 使用诸如符号串搜索模块的小型硬件规模处理模块来高速执行字符串搜索算术运算。 搜索模块通过地址和数据总线连接到CPU，并且包括用于根据来自CPU的命令定义设备的功能的功能定义部分，用于接收要搜索的符号串的数据输入/输出部分 数据总线并输出搜索结果。 搜索处理部分基于由功能定义部分定义的功能来执行搜索。 将内部存储的要搜索的符号串与输入到模块的数据输入/输出装置的符号串数据进行比较。 条件保持部分保存指示与搜索处理结果相对应的内部条件的数据。 因此，CPU和符号串搜索模块可以高速执行搜索。

公开(公告)号：US4918686A

公开(公告)日：1990-04-17

申请号：US224894

申请日：1988-07-27

申请人： Takehisa Hayashi ,  Koichiro Omada ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

发明人： Takehisa Hayashi ,  Koichiro Omada ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

IPC分类号： H04L12/935 ,  H04L12/937

CPC分类号： H04L49/3018 ,  H04L49/254 ,  H04L49/3027

摘要： In a data transfer network of the present invention, each switch is designed such that when the partial address necessary for a given switch to determine another switch belonging to the succeeding stage, to which a packet is to be delivered from the given switch, is included in the first one of plural subpackets supplied to the given switch and each having the partial address, the given switch starts its switching operation upon arrival of the first subpacket. In a preferred embodiment, when the partial address necessary for the succeeding switch to make its switching operation is not included in the first subpacket, the partial addresses are exchanged between the subpackets by the preceding switch so that the said partial address is now included in the first subpacket.

摘要翻译： 在本发明的数据传输网络中，每个交换机被设计成使得当给定交换机所需的部分地址被确定为属于后一级的另一交换机时，包括从给定交换机向其传送分组的部分地址 在提供给给定开关并且每个具有部分地址的多个子分组中的第一个子分组中，给定开关在第一子分组到达时开始其切换操作。 在优选实施例中，当后续交换机进行其切换操作所需的部分地址不包括在第一子分组中时，通过前一交换机在子分组之间交换部分地址，使得所述部分地址现在包括在 第一个子分组

公开(公告)号：US4697110A

公开(公告)日：1987-09-29

申请号：US555618

申请日：1983-11-28

申请人： Noboru Masuda ,  Michio Asano ,  Takehisa Hayashi ,  Hirotoshi Tanaka ,  Akira Masaki

发明人： Noboru Masuda ,  Michio Asano ,  Takehisa Hayashi ,  Hirotoshi Tanaka ,  Akira Masaki

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0952 ,  H03K17/14 ,  H03K19/094

CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

摘要： An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.

摘要翻译： 用于半导体电路的输入缓冲器设置有源极跟随器电路，该源极跟随器电路由其栅极具有与其连接的输入端的第一FET和与第一FET的导电类型相同的第二FET组成，漏极连接到 直接或通过至少一个电平移位二极管的第一FET的源极，并且其栅电极被提供控制电压。 输入缓冲器还包括直接或通过至少一个电平移位二极管连接到第二FET的漏电极的FET反相器电路。 输入缓冲器的输出信号是从FET反相器电路得出的。 本发明的一个特别优点在于，它允许输入缓冲器响应于处于预定电压范围内的输入信号而将其输出从一个电平切换到另一个电平，而与FET中的逻辑阈值电平波动无关，并且耦合到 输入缓冲区。