摘要:
A nonvolatile memory array has two or more stacked layers of memory cells (10). The bottom layer may comprise a planar, X-cell, or buried N++ FAMOS transistor array and the top layer preferably comprises a planar transistor array. An epitaxial silicon layer (36) provides the substrate for the second layer. The stacked layer structure allows a two-fold increase in memory density without scaling the device sizes.
摘要:
An EEPROM memory cell having sidewall floating gates (28, 28a, 28b) is disclosed. Sidewall floating gates (28, 28a, 28b) are formed on sidewalls (30, 32) of a central block (22). Spaced apart bit lines (36, 36a, 36b) are formed to serve as memory cell sources and drains. Sidewall floating gates (28a, 28b) are capable of being programmed independently of one another. When control gate (18) is actuated and either bit line (36a) or bit line (36b) is used to read the device, four separate memory states may be identified depending on whether either, neither or both of the sidewall floating gates (28a, 28b) have been programmed.
摘要:
Bitlines (34) are formed by creating a diffused region (26) around the sidewalls and bottom of a trench (20). The trench (20) is filled with a conductive region (30), typically a refractory metal, refractory metal silicide.
摘要:
One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.
摘要:
A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implants of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.
摘要:
A method and apparatus for providing interconnections between levels on a semiconductor substrate of various types includes first forming a plurality of trenches in the substrate and then forming conductive layers at the bottom of the trenches. The trenches are then filled with an oxide to provide a planar surface on the substrate. Various levels of trenches are provided with crossovers being formed by a bridging layer of a conductive material that is formed over an oxide layer in the lower level trenches. Vertical contacts are formed by etching an opening from the surface to the bottom of the trenches through the oxide layer and filling the opening with a metal plug.
摘要:
A non-volatie cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines form the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.
摘要:
Using a method according to one embodiment of the present invention, an EPROM array may be fabricated providing a dense EPROM array.First the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1 to 1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface. The silicon dioxide layer is then further etched so that the top surfaces of the floating gates are exposed. An interlevel insulator layer is then formed on the surface of the array and the active gates are then formed on the surface of the interlevel insulator.In another embodiment of the present invention, a step for forming refractory metal silicide regions on the bitlines of the array is included. The use of silicided bitlines in this type of array is precluded in the prior art because thick field oxide regions must be thermally grown over the silicided regions using the prior art techniques. The growth of silicon dioxide over silicided regions is very difficult if not impossible.
摘要:
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
摘要:
In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.