Method of forming a nonvolatile stacked memory
    41.
    发明授权
    Method of forming a nonvolatile stacked memory 失效
    形成非易失性堆叠存储器的方法

    公开(公告)号:US5306935A

    公开(公告)日:1994-04-26

    申请号:US900225

    申请日:1992-06-17

    摘要: A nonvolatile memory array has two or more stacked layers of memory cells (10). The bottom layer may comprise a planar, X-cell, or buried N++ FAMOS transistor array and the top layer preferably comprises a planar transistor array. An epitaxial silicon layer (36) provides the substrate for the second layer. The stacked layer structure allows a two-fold increase in memory density without scaling the device sizes.

    摘要翻译: 非易失性存储器阵列具有两个或多个层叠的存储器单元(10)。 底层可以包括平面的X电池或埋入的N ++ FAMOS晶体管阵列,并且顶层优选地包括平面晶体管阵列。 外延硅层(36)为第二层提供衬底。 堆叠层结构允许存储器密度增加两倍,而不缩放器件尺寸。

    Four memory state EEPROM
    42.
    发明授权
    Four memory state EEPROM 失效
    四个内存状态EEPROM

    公开(公告)号:US5159570A

    公开(公告)日:1992-10-27

    申请号:US697228

    申请日:1991-05-07

    摘要: An EEPROM memory cell having sidewall floating gates (28, 28a, 28b) is disclosed. Sidewall floating gates (28, 28a, 28b) are formed on sidewalls (30, 32) of a central block (22). Spaced apart bit lines (36, 36a, 36b) are formed to serve as memory cell sources and drains. Sidewall floating gates (28a, 28b) are capable of being programmed independently of one another. When control gate (18) is actuated and either bit line (36a) or bit line (36b) is used to read the device, four separate memory states may be identified depending on whether either, neither or both of the sidewall floating gates (28a, 28b) have been programmed.

    摘要翻译: 公开了一种具有侧壁浮动栅极(28,28a,28b)的EEPROM存储单元。 侧壁浮动门(28,28a,28b)形成在中心块(22)的侧壁(30,32)上。 间隔开的位线(36,36a,36b)形成为用作存储器单元源和漏极。 侧壁浮动门(28a,28b)能够被彼此独立地编程。 当控制栅极(18)被启动并且位线(36a)或位线(36b)被用于读取器件时,可以根据侧壁浮动栅极(28a)或两者之一 ,28b)已被编程。

    Floating gate memory cell and device
    44.
    发明授权
    Floating gate memory cell and device 失效
    浮栅存储单元和器件

    公开(公告)号:US5053839A

    公开(公告)日:1991-10-01

    申请号:US570944

    申请日:1990-08-21

    摘要: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

    摘要翻译: 本发明的一个实施例提供一种EPROM和一种制造具有增强的电容耦合的EPROM的方法。 每个沟槽的存储单元都包括褶状浮动栅极,其中控制栅极嵌套在浮动栅极的折叠中,以增加与控制栅极的耦合比。 因此,对于给定的编程电压,可以获得更高的编程速度和改善的单元密度。 沿着沟槽壁的位线的形成导致给定电池密度的较低的位线电阻率。

    Floating-gate memory cell with tailored doping profile
    45.
    发明授权
    Floating-gate memory cell with tailored doping profile 失效
    具有定制掺杂特性的浮栅存储单元

    公开(公告)号:US4979005A

    公开(公告)日:1990-12-18

    申请号:US889454

    申请日:1986-07-23

    申请人: Allan T. Mitchell

    发明人: Allan T. Mitchell

    CPC分类号: H01L29/105 H01L29/7885

    摘要: A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implants of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.

    摘要翻译: 具有改进的掺杂分布的浮栅存储器单元。 在将衬底背景掺杂设置为期望水平(例如通过高剂量注入和长驱动)之后,使用相反类型的两个注入来形成浮栅晶体管的掺杂分布。 使用硼注入来在源/漏扩散的中点附近的深度处提供在通道下方的显着增加的p型掺杂。 浅砷植入物在表面部分地补偿该硼注入,以根据需要设定阈值电压。 大大增加的p型掺杂的区域有助于抑制否则可以抑制编程的横向寄生双极晶体管,并且(通过在漏极边界处提供增加的掺杂)增加热电子产生。

    Buried multilevel interconnect system
    46.
    发明授权
    Buried multilevel interconnect system 失效
    埋地多层互连系统

    公开(公告)号:US4977439A

    公开(公告)日:1990-12-11

    申请号:US34305

    申请日:1987-04-03

    摘要: A method and apparatus for providing interconnections between levels on a semiconductor substrate of various types includes first forming a plurality of trenches in the substrate and then forming conductive layers at the bottom of the trenches. The trenches are then filled with an oxide to provide a planar surface on the substrate. Various levels of trenches are provided with crossovers being formed by a bridging layer of a conductive material that is formed over an oxide layer in the lower level trenches. Vertical contacts are formed by etching an opening from the surface to the bottom of the trenches through the oxide layer and filling the opening with a metal plug.

    摘要翻译: 用于在各种类型的半导体衬底上提供电平之间的互连的方法和装置包括首先在衬底中形成多个沟槽,然后在沟槽的底部形成导电层。 然后用氧化物填充沟槽,以在衬底上提供平坦的表面。 提供了各种级别的沟槽,其中沟道由形成在下层沟槽中的氧化物层上的导电材料的桥接层形成。 通过蚀刻通过氧化物层从沟槽的表面到底部的开口并用金属插塞填充开口来形成垂直触点。

    Fast, trench isolated, planar flash EEPROMS with silicided bitlines
    47.
    发明授权
    Fast, trench isolated, planar flash EEPROMS with silicided bitlines 失效
    快速,沟槽隔离,平面闪光EEPROMS与硅化位线

    公开(公告)号:US4951103A

    公开(公告)日:1990-08-21

    申请号:US202766

    申请日:1988-06-03

    IPC分类号: H01L27/115 H01L29/788

    CPC分类号: H01L27/115 H01L29/7883

    摘要: A non-volatie cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines form the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.

    摘要翻译: 非挥发性交叉点存储单元阵列包括存储器单元(10)的沟槽隔离交叉点阵列,其被电可编程且电闪存可擦除,其具有可操作为位线的扩散区域(28),每个扩散区域(28) 由可操作为字线的多个控制门(54)穿过。 扩散区域(28)进行硅化处理以降低其电阻率,从而增加存储单元阵列的速度。 提供隧道氧化物(18)用于电擦除和编程。 平面化的高品质绝缘区域(40,36),例如二氯硅烷氧化物,支撑浮动栅极(20),以将字线与字线隔离开来,并改善栅极与浮栅之间的隔离。 存储单元(10)的平面结构为三维堆叠结构提供了理想的平坦地形。 沟槽隔离区(56)可减少位线电容,从而提高编程速度。

    EPROM array and method for fabricating
    48.
    发明授权
    EPROM array and method for fabricating 失效
    EPROM阵列及其制造方法

    公开(公告)号:US4597060A

    公开(公告)日:1986-06-24

    申请号:US729439

    申请日:1985-05-01

    CPC分类号: H01L27/11521

    摘要: Using a method according to one embodiment of the present invention, an EPROM array may be fabricated providing a dense EPROM array.First the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1 to 1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface. The silicon dioxide layer is then further etched so that the top surfaces of the floating gates are exposed. An interlevel insulator layer is then formed on the surface of the array and the active gates are then formed on the surface of the interlevel insulator.In another embodiment of the present invention, a step for forming refractory metal silicide regions on the bitlines of the array is included. The use of silicided bitlines in this type of array is precluded in the prior art because thick field oxide regions must be thermally grown over the silicided regions using the prior art techniques. The growth of silicon dioxide over silicided regions is very difficult if not impossible.

    摘要翻译: 使用根据本发明的一个实施例的方法,可以制造提供密集的EPROM阵列的EPROM阵列。 首先,在衬底的表面上形成并部分地构图多晶硅浮栅。 然后在整个阵列上形成薄的热生长氧化物层。 然后将源极/漏极区域通过薄的二氧化硅层注入到衬底中。 接下来,通过化学气相沉积在阵列的表面上沉积厚的二氧化硅层。 然后将阵列的表面涂覆有光致抗蚀剂,由于其性质,其在光致抗蚀剂的顶层上提供平坦化的表面。 然后使用在光致抗蚀剂和二氧化硅之间提供1至1的蚀刻比的蚀刻工艺来蚀刻光致抗蚀剂和二氧化硅层。 光致抗蚀剂被完全蚀刻掉,从而留下平坦化的二氧化硅表面。 然后进一步蚀刻二氧化硅层,使得浮动栅极的顶表面露出。 然后在阵列的表面上形成层间绝缘体层,然后在层间绝缘体的表面上形成有源栅极。 在本发明的另一个实施例中,包括在阵列的位线上形成难熔金属硅化物区域的步骤。 在现有技术中排除了在这种类型的阵列中使用硅化位线,因为厚场氧化物区域必须使用现有技术在硅化区域上热生长。 二氧化硅在硅化物区域的增长是非常困难的,如果不是不可能的话。

    Analog floating-gate memory with N-channel and P-channel MOS transistors
    49.
    发明授权
    Analog floating-gate memory with N-channel and P-channel MOS transistors 有权
    具有N沟道和P沟道MOS晶体管的模拟浮栅存储器

    公开(公告)号:US08981445B2

    公开(公告)日:2015-03-17

    申请号:US13406704

    申请日:2012-02-28

    摘要: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

    摘要翻译: 集成电路中的模拟浮栅电极及其制造方法,其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平,在其整个长度上掺杂n型,并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区,设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层,而集成电路中的其它多晶硅结构是硅化物包覆的。

    Non-volatile anti-fuse with consistent rupture
    50.
    发明授权
    Non-volatile anti-fuse with consistent rupture 有权
    不挥发性反熔丝具有一致的破裂

    公开(公告)号:US08748235B2

    公开(公告)日:2014-06-10

    申请号:US13569730

    申请日:2012-08-08

    IPC分类号: H01L21/336

    摘要: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

    摘要翻译: 在本发明的实施例中,公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分,其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时,在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。