公开(公告)号：US4833514A

公开(公告)日：1989-05-23

申请号：US121980

申请日：1987-11-18

申请人： Agerico L. Esquivel ,  Allan T. Mitchell

发明人： Agerico L. Esquivel ,  Allan T. Mitchell

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1:1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface. The silicon dioxide layer is then further etched so that the top surfaces of the floating gates are exposed. An interlevel insulator layer is then formed on the surface of the array and the active gates are then formed on the surface of the interlevel insulator.

摘要翻译： 本发明提供一种具有高质量电介质的EPROM，通过下面概述的方法将浮动栅极与现有技术中使用的低质量电介质层分离。 首先，在衬底的表面上形成多晶硅浮栅并部分地构图。 然后在整个阵列上形成薄的热生长氧化物层。 然后将源极/漏极区域通过薄的二氧化硅层注入到衬底中。 接下来，通过化学气相沉积在阵列的表面上沉积厚的二氧化硅层。 然后将阵列的表面涂覆有光致抗蚀剂，由于其性质，其在光致抗蚀剂的顶层上提供平坦化的表面。 然后使用在光致抗蚀剂和二氧化硅之间提供1：1的蚀刻比的蚀刻工艺来蚀刻光致抗蚀剂和二氧化硅层。 光致抗蚀剂被完全蚀刻掉，从而留下平坦化的二氧化硅表面。 然后进一步蚀刻二氧化硅层，使得浮动栅极的顶表面露出。 然后在阵列的表面上形成层间绝缘体层，然后在层间绝缘体的表面上形成有源栅极。

公开(公告)号：US5045490A

公开(公告)日：1991-09-03

申请号：US570655

申请日：1990-08-21

申请人： Agerico L. Esquivel ,  Allan T. Mitchell ,  Howard L. Tigelaar

发明人： Agerico L. Esquivel ,  Allan T. Mitchell ,  Howard L. Tigelaar

IPC分类号： H01L27/115 ,  H01L29/08 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L29/0847

摘要： One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit lines resistivity for a given cell density.

摘要翻译： 本发明的一个实施例提供一种EPROM和一种制造具有增强的电容耦合的EPROM的方法。 每个沟槽的存储单元都包括褶状浮动栅极，其中控制栅极嵌套在浮动栅极的折叠中，以增加与控制栅极的耦合比。 因此，对于给定的编程电压，可以获得更高的编程速度和改善的单元密度。 沿着沟槽壁的位线形成导致给定电池密度的较低的位线电阻率。

公开(公告)号：US4905062A

公开(公告)日：1990-02-27

申请号：US312398

申请日：1989-02-17

申请人： Agerico L. Esquivel ,  Allan T. Mitchell

发明人： Agerico L. Esquivel ,  Allan T. Mitchell

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7886

摘要： A sealed gate FAMOS transistor (28) disposes a thermal oxide layer (40) about the floating gate (34) in order to isolate the floating gate (34) from the planar isolating regions (44) between floating gates (34). Trench isolating regions (54) are provided between control gates (50) to enhance programmability of the sealed gate FAMOS transistor (28).

摘要翻译： 密封栅极FAMOS晶体管（28）围绕浮动栅极（34）设置热氧化物层（40），以将浮动栅极（34）与浮置栅极（34）之间的平面隔离区域（44）隔离。 沟槽隔离区域（54）设置在控制栅极（50）之间，以增强密封栅极FAMOS晶体管（28）的可编程性。

公开(公告)号：US4892840A

公开(公告)日：1990-01-09

申请号：US336265

申请日：1989-04-11

申请人： Agerico L. Esquivel ,  Robert Groover, III ,  Howard L. Tigelaar

发明人： Agerico L. Esquivel ,  Robert Groover, III ,  Howard L. Tigelaar

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76216 ,  H01L21/76224 ,  H01L27/115

摘要： Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

摘要翻译： 公开了具有高速编程能力的浮动栅极存储器阵列。 扩散掩埋位线（14）在半导体中间隔开形成，在其间形成传导通道。 介电填充沟槽（24）形成在位线（14）之间。 绝缘浮栅导体（18）和绝缘控制栅极导体（23）形成在晶片之上并被图案化以在电介质填充的沟槽（24）上延伸。 控制栅极（23）和浮动栅极（18）之间增强的耦合效率提高了存储器单元的可编程性。

公开(公告)号：US06201277B1

公开(公告)日：2001-03-13

申请号：US08484196

申请日：1995-06-07

申请人： Agerico L. Esquivel

发明人： Agerico L. Esquivel

IPC分类号： H01L29788

CPC分类号： H01L27/11519 ,  H01L21/76237 ,  H01L27/115 ,  H01L27/11521

摘要： A programmable memory device having slot trenches (14). A plurality of floating gates (22) are separated from a surface of semiconductor body (10) by a gate dielectric (24). A plurality of slot trenches (14) isolate memory cells (12) from each other. Each of the slot trenches (14) extends below the surface of the semiconductor body (10) between adjacent floating gates (22). A control gate (20) extends over the floating gates (22) and a portion of each of the slot trenches (14).

摘要翻译： 一种具有槽槽（14）的可编程存储器件。 多个浮动栅极（22）通过栅极电介质（24）与半导体本体（10）的表面分离。 多个时隙沟槽（14）隔离存储器单元（12）。 每个槽沟（14）在相邻的浮动栅极（22）之间的半导体本体（10）的表面的下方延伸。 控制栅极（20）在浮动栅极（22）和每个槽沟槽（14）的一部分之上延伸。

公开(公告)号：US5028553A

公开(公告)日：1991-07-02

申请号：US533635

申请日：1990-06-05

申请人： Agerico L. Esquivel ,  Allan T. Mitchell

发明人： Agerico L. Esquivel ,  Allan T. Mitchell

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L29/7883 ,  H01L27/115 ,  Y10S148/147

摘要： A non-volatile cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines from the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.

摘要翻译： 非易失性交叉点存储单元阵列包括存储器单元（10）的沟槽隔离交叉点阵列，其可电可编程且电闪存可擦除，其具有可操作为位线的扩散区域（28），每个扩散区域（28） 由可操作为字线的多个控制门（54）穿过。 扩散区域（28）进行硅化处理以降低其电阻率，从而增加存储单元阵列的速度。 提供隧道氧化物（18）用于电擦除和编程。 平面化的高品质绝缘区域（40,36），例如二氯硅烷氧化物，支撑浮动栅极（20）以将位线与字线隔离，并改善栅极与浮栅之间的隔离。 存储单元（10）的平面结构为三维堆叠结构提供了平坦的地形理想的。 沟槽隔离区（56）可减少位线电容，从而提高编程速度。

公开(公告)号：US5008722A

公开(公告)日：1991-04-16

申请号：US363366

申请日：1989-05-31

申请人： Agerico L. Esquivel

发明人： Agerico L. Esquivel

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76216 ,  H01L21/76224 ,  H01L27/115 ,  Y10S257/903

摘要： A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor. This results in improved leakage current, improved punchthrough voltage characteristics, and in improved programmability for the cell.

摘要翻译： 交叉点EPROM阵列具有沟槽，以在相邻的掩埋N +位线未被​​FAMOS晶体管分离的位置处提供相邻的掩埋N +位线之间的改进的隔离。 这导致改善的漏电流，改进的穿透电压特性以及改进的电池可编程性。

公开(公告)号：US4979004A

公开(公告)日：1990-12-18

申请号：US469814

申请日：1990-01-23

申请人： Agerico L. Esquivel ,  Allan T. Mitchell ,  Howard L. Tigelaar

发明人： Agerico L. Esquivel ,  Allan T. Mitchell ,  Howard L. Tigelaar

IPC分类号： H01L27/115 ,  H01L29/08 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L29/0847

摘要： One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

摘要翻译： 本发明的一个实施例提供一种EPROM和一种制造具有增强的电容耦合的EPROM的方法。 每个沟槽的存储单元都包括褶状浮动栅极，其中控制栅极嵌套在浮动栅极的折叠中，以增加与控制栅极的耦合比。 因此，对于给定的编程电压，可以获得更高的编程速度和改善的单元密度。 沿着沟槽壁的位线的形成导致给定电池密度的较低的位线电阻率。

公开(公告)号：US4698900A

公开(公告)日：1987-10-13

申请号：US844915

申请日：1986-03-27

申请人： Agerico L. Esquivel

发明人： Agerico L. Esquivel

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/70 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76216 ,  H01L21/76224 ,  H01L27/115 ,  Y10S148/05

摘要： A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor. This results in improved leakage current, improved punchthrough voltage characteristics, and in improved programmability for the cell.

摘要翻译： 交叉点EPROM阵列具有沟槽，以在相邻的掩埋N +位线未被​​FAMOS晶体管分离的位置处提供相邻的掩埋N +位线之间的改进的隔离。 这导致改善的漏电流，改进的穿透电压特性以及改进的电池可编程性。

公开(公告)号：US5306935A

公开(公告)日：1994-04-26

申请号：US900225

申请日：1992-06-17

申请人： Agerico L. Esquivel ,  Allan T. Mitchell

发明人： Agerico L. Esquivel ,  Allan T. Mitchell

IPC分类号： H01L21/822 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551

摘要： A nonvolatile memory array has two or more stacked layers of memory cells (10). The bottom layer may comprise a planar, X-cell, or buried N++ FAMOS transistor array and the top layer preferably comprises a planar transistor array. An epitaxial silicon layer (36) provides the substrate for the second layer. The stacked layer structure allows a two-fold increase in memory density without scaling the device sizes.

摘要翻译： 非易失性存储器阵列具有两个或多个层叠的存储器单元（10）。 底层可以包括平面的X电池或埋入的N ++ FAMOS晶体管阵列，并且顶层优选地包括平面晶体管阵列。 外延硅层（36）为第二层提供衬底。 堆叠层结构允许存储器密度增加两倍，而不缩放器件尺寸。