公开(公告)号：US20120329216A1

公开(公告)日：2012-12-27

申请号：US13229266

申请日：2011-09-09

申请人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Erik Maki ,  Jason Gurganus ,  Daniel Jenner Lichtenwalner

发明人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Erik Maki ,  Jason Gurganus ,  Daniel Jenner Lichtenwalner

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/02378 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7813

摘要： Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

摘要翻译： 公开了具有增加的信道移动性的半导体器件及其制造方法的实施例。 在一个实施例中，半导体器件包括在沟道区上的衬底上包括沟道区和栅叠层的衬底。 栅极堆叠包括碱土金属。 在一个实施方案中，碱土金属是钡（Ba）。 在另一个实施方案中，碱土金属是锶（Sr）。 碱土金属导致半导体器件的沟道迁移率的显着改善。

公开(公告)号：US08330244B2

公开(公告)日：2012-12-11

申请号：US12492670

申请日：2009-06-26

申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07

CPC分类号： H01L29/0619 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.

摘要翻译： 根据一些实施例的半导体器件包括具有第一导电类型的半导体层和限定半导体器件的有源区的表面。 多个间隔开的第一掺杂区域被布置在有源区域内。 多个第一掺杂区域具有与第一导电类型相反的第二导电类型，具有第一掺杂剂浓度，并且在有源区内限定半导体层的多个暴露部分。 多个第一掺杂区域在半导体层中被布置为岛状。 半导体层中的第二掺杂区域具有第二导电类型并且具有大于第一掺杂剂浓度的第二掺杂剂浓度。

公开(公告)号：US20120280270A1

公开(公告)日：2012-11-08

申请号：US13108440

申请日：2011-05-16

申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

摘要翻译： 半导体器件包括具有第一导电类型的漂移层，漂移层中具有与第一导电类型相反的第二导电类型的阱区以及阱区中的源极区。源极区具有第一导电类型并且限定 在井区域中的通道区域。 源极区域包括与沟道区域相邻的横向源极区域和远离与沟道区域相对的横向源极区域延伸的多个源极接触区域。 具有第二导电类型的体接触区域在多个源极接触区域中的至少两个之间并且与阱区域接触。 源欧姆触点与源极接触区域和身体接触区域中的至少一个重叠。 半导体器件的源极接触区域的最小尺寸由源极欧姆接触和至少一个源极接触区域之间的重叠区域限定。

公开(公告)号：US20080029838A1

公开(公告)日：2008-02-07

申请号：US11496842

申请日：2006-08-01

申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

IPC分类号： H01L29/47

CPC分类号： H01L29/0619 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A semiconductor device includes a semiconductor layer having a first conductivity type, a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer, and a semiconductor region in the semiconductor layer. The semiconductor region and the semiconductor layer form a first p-n junction in parallel with the Schottky junction. The first p-n junction is configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to thereby limit reverse leakage current through the Schottky junction. The first p-n junction is further configured such that punch-through of the first p-n junction occurs at a lower voltage than a breakdown voltage of the Schottky junction when the Schottky junction is reverse biased.

摘要翻译： 半导体器件包括具有第一导电类型的半导体层，半导体层上的金属接触并与半导体层形成肖特基结，以及半导体层中的半导体区域。 半导体区域和半导体层与肖特基结并联形成第一p-n结。 第一p-n结被配置为当肖特基结被反向偏置时在与肖特基结相邻的半导体层中产生耗尽区，从而限制通过肖特基结的反向漏电流。 第一p-n结进一步配置成使得当肖特基结被反向偏置时，第一p-n结的穿通以比肖特基结的击穿电压低的电压发生。

公开(公告)号：US20070145378A1

公开(公告)日：2007-06-28

申请号：US11315672

申请日：2005-12-22

申请人： Anant Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  D. Capell

发明人： Anant Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  D. Capell

IPC分类号： H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/1004 ,  H01L29/7325

摘要： A bipolar junction transistor (BJT) includes a silicon carbide (SiC) collector layer of first conductivity type, an epitaxial silicon carbide base layer of second conductivity type on the silicon carbide collector layer, and an epitaxial silicon carbide emitter mesa of the first conductivity type on the epitaxial silicon carbide base layer. An epitaxial silicon carbide passivation layer of the first conductivity type is provided on at least a portion of the epitaxial silicon carbide base layer outside the silicon carbide emitter mesa. The epitaxial silicon carbide passivation layer can be configured to fully deplete at zero device bias. Related fabrication methods also are disclosed.

摘要翻译： 双极结型晶体管（BJT）包括第一导电类型的碳化硅（SiC）集电极层，在碳化硅集电极层上的第二导电类型的外延碳化硅基底层和第一导电类型的外延碳化硅发射极台面 在外延碳化硅基底层上。 第一导电类型的外延碳化硅钝化层设置在碳化硅发射极台面外部的外延碳化硅基底层的至少一部分上。 外延碳化硅钝化层可以被配置为在零器件偏置下完全耗尽。 还公开了相关的制造方法。

公开(公告)号：US20060261346A1

公开(公告)日：2006-11-23

申请号：US11131880

申请日：2005-05-18

申请人： Sei-Hyung Ryu ,  Jason Jenny ,  Mrinal Das ,  Anant Agarwal ,  John Palmour ,  Hudson Hobgood

发明人： Sei-Hyung Ryu ,  Jason Jenny ,  Mrinal Das ,  Anant Agarwal ,  John Palmour ,  Hudson Hobgood

IPC分类号： H01L31/0312

CPC分类号： H01L29/74 ,  H01L21/0465 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/41716 ,  H01L29/66068 ,  H01L29/747

摘要： High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer, has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface of the voltage blocking SiC substrate. A third region of SiC is provided on the second SiC layer and has the second conductivity type. A fourth region of SiC is provided in the second SiC layer, has the first conductivity type and is adjacent to the third region of SiC. First and second contacts are provided on the first and third regions of SiC, respectively. Related methods of fabricating high voltage SiC devices are also provided.

公开(公告)号：US20060261345A1

公开(公告)日：2006-11-23

申请号：US11131509

申请日：2005-05-18

申请人： Sei-Hyung Ryu ,  Jason Jenny ,  Mrinal Das ,  Hudson Hobgood ,  Anant Agarwal ,  John Palmour

发明人： Sei-Hyung Ryu ,  Jason Jenny ,  Mrinal Das ,  Hudson Hobgood ,  Anant Agarwal ,  John Palmour

IPC分类号： H01L31/0312

CPC分类号： H01L29/74 ,  H01L29/0661 ,  H01L29/1608

摘要： High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer. The second region of SiC has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface, opposite the first surface, of the voltage blocking SiC substrate. First, second and third contacts are provided on the first region of SiC, the second region of SiC and the second SiC layer, respectively. Related methods of fabricating high voltage SiC devices are also provided.

摘要翻译： 提供高压碳化硅（SiC）器件，例如晶闸管。 具有第一导电类型的第一SiC层设置在具有第二导电类型的压电SiC衬底的第一表面上。 SiC的第一区域设置在第一SiC层上并具有第二导电类型。 SiC的第二区域设置在第一SiC层中。 SiC的第二区域具有第一导电类型并且与SiC的第一区域相邻。 具有第一导电类型的第二SiC层设置在压电SiC衬底的与第一表面相对的第二表面上。 首先，分别在SiC的第一区域，SiC的第二区域和第二SiC层上设置第二和第三触点。 还提供了制造高电压SiC器件的相关方法。

公开(公告)号：US20060118792A1

公开(公告)日：2006-06-08

申请号：US11331325

申请日：2006-01-12

申请人： Sei-Hyung Ryu ,  Anant Agarwal ,  Allan Ward

发明人： Sei-Hyung Ryu ,  Anant Agarwal ,  Allan Ward

IPC分类号： H01L31/0312

CPC分类号： H01L29/0619 ,  H01L21/0445 ,  H01L23/3192 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An edge termination structure for a silicon carbide semiconductor device includes a plurality of spaced apart concentric floating guard rings in a silicon carbide layer that at least partially surround a silicon carbide-based junction, an insulating layer on the floating guard rings, and a silicon carbide surface charge compensation region between the floating guard rings and adjacent the surface of the silicon carbide layer. A silicon nitride layer is on the silicon carbide layer, and an organic protective layer is on the silicon nitride layer. An oxide layer may be between the silicon nitride layer and the surface of the silicon carbide layer. Methods of forming edge termination structures are also disclosed.

摘要翻译： 用于碳化硅半导体器件的边缘终端结构包括在碳化硅层中的至少部分地围绕碳化硅基结的多个间隔开的同心浮动保护环，浮动保护环上的绝缘层和碳化硅 浮动保护环之间的表面电荷补偿区域与碳化硅层表面相邻。 氮化硅层位于碳化硅层上，有机保护层位于氮化硅层上。 氧化物层可以在氮化硅层和碳化硅层的表面之间。 还公开了形成边缘端接结构的方法。

公开(公告)号：US09009660B1

公开(公告)日：2015-04-14

申请号：US11564723

申请日：2006-11-29

申请人： Patrick Robert Griffin ,  Walter Lee ,  Anant Agarwal ,  David Wentzlaff

发明人： Patrick Robert Griffin ,  Walter Lee ,  Anant Agarwal ,  David Wentzlaff

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F9/48

CPC分类号： G06F8/445 ,  G06F8/30 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/437 ,  G06F8/447 ,  G06F8/451 ,  G06F8/453 ,  G06F9/48 ,  G06F9/546 ,  G06F2209/548

摘要： Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.

摘要翻译： 在多处理器环境中的编程包括接受定义多个处理模块的程序规范和用于在模块的端口之间发送数据的一个或多个通道，将每个处理模块映射到一组一个或多个处理引擎上 互联处理引擎的网络，以及至少一些信道，将网络中的一个或多个处理引擎的一个或多个元素分配给用于在各个处理模块之间发送数据的信道。

公开(公告)号：US08211770B2

公开(公告)日：2012-07-03

申请号：US13167806

申请日：2011-06-24

申请人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

发明人： Qingchun Zhang ,  Anant Agarwal ,  Charlotte Jonas

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/749 ,  H01L29/7828

摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

摘要翻译： 晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。 由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区，AMOSFET进一步显示出高电压阻断能力。 除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。 掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。 电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。 沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。