公开(公告)号：US06346824B1

公开(公告)日：2002-02-12

申请号：US09627247

申请日：2000-07-27

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： G06F738

CPC分类号： G06F7/5324 ,  H03K19/17732 ,  H03K19/17736

摘要： A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of dedicated function blocks. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the array of function blocks. However, selected CLEs can also be coupled to selected function blocks, thereby creating a relatively high density circuit to implement the dedicated function. The function blocks can be selectively coupled to one another, such that the function blocks are connected to form a relatively large circuit. The desired input signals are routed into the function blocks from associated CLEs. Similarly, the resulting output signals are routed from the function blocks to associated CLEs. In this manner, the FPGA is capable of implementing a relatively large circuit having the dedicated function in an efficient manner.

摘要翻译： 可编程逻辑器件，例如现场可编程门阵列（FPGA），其包括可配置逻辑元件（CLE）的阵列和相应的专用功能块阵列。 CLE可以作为传统的可配置逻辑元件操作，与功能块阵列完全断开连接。 然而，所选择的CLE也可以耦合到所选择的功能块，从而产生相对高密度的电路来实现专用功能。 功能块可以选择性地彼此耦合，使得功能块被连接以形成相对较大的电路。 期望的输入信号从相关联的CLE路由到功能块中。 类似地，所得到的输出信号从功能块路由到相关联的CLE。 以这种方式，FPGA能够以有效的方式实现具有专用功能的相对较大的电路。

公开(公告)号：US06288570B1

公开(公告)日：2001-09-11

申请号：US09679151

申请日：2000-10-03

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： H03K19177

CPC分类号： G06F7/503 ,  G06F7/507 ,  G06F2207/4812 ,  H03K19/1737

摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.

摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。 对于每个位，进位传播信号由查找表可编程函数发生器产生，并被专用硬件用于生成进位信号。

公开(公告)号：US06184709B2

公开(公告)日：2001-02-06

申请号：US09105188

申请日：1998-06-26

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： H03K19177

CPC分类号： H03K19/1776

摘要： A programmable logic device (PLD) which includes a dedicated composable RAM array having a plurality of memory tiles. The PLD also includes an array of CLBs, wherein each of the CLBs in the array is coupled to a corresponding one of the memory tiles. The composable RAM array is accessed through the CLBs. That is, the input signals required by the memory tiles are routed through the corresponding CLBs. Similarly, the output signals provided by the memory tiles are routed out through the corresponding CLBs. Each CLB can be configured to operate as a conventional CLB (i.e., ignore its corresponding memory tile). Alternatively, each CLB can be configured to provide an interface to its corresponding memory tile. To help achieve this, each CLB comprises a set of multiplexers for selectively routing data output signals provided by the corresponding memory tile or output signals provided by the CLB. In addition, each memory tile is capable of being selectively coupled to one or more adjacent memory tiles, thereby allowing the size of the composable RAM array to be selected by the circuit designer. This capability also allows the composable RAM array to be configured to form a plurality of separate and independent memories.

摘要翻译： 一种可编程逻辑器件（PLD），其包括具有多个存储器片的专用可组合RAM阵列。 PLD还包括一组CLB，其中阵列中的每个CLB耦合到相应的一个存储器片。 可组合的RAM阵列通过CLB访问。 也就是说，存储器片所需的输入信号通过相应的CLB路由。 类似地，由存储器片提供的输出信号通过相应的CLB被路由输出。 每个CLB可以被配置为作为常规CLB（即忽略其对应的存储器块）来操作。 或者，每个CLB可以被配置为向其对应的存储器块提供接口。 为了帮助实现这一点，每个CLB包括一组多路复用器，用于选择性地路由由相应的存储器块提供的数据输出信号或由CLB提供的输出信号。 此外，每个存储器片能够被选择性地耦合到一个或多个相邻的存储器片，从而允许由电路设计者选择可组合的RAM阵列的大小。 该功能还允许可组合的RAM阵列被配置成形成多个独立且独立的存储器。

公开(公告)号：US06150839A

公开(公告)日：2000-11-21

申请号：US504468

申请日：2000-02-16

申请人： Bernard J. New ,  Robert Anders Johnson ,  Ralph Wittig ,  Sundarajarao Mohan

发明人： Bernard J. New ,  Robert Anders Johnson ,  Ralph Wittig ,  Sundarajarao Mohan

IPC分类号： H03K19/177

CPC分类号： H03K19/17752 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17796

摘要： A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

摘要翻译： 包括可配置逻辑块的第一和第二阵列的现场可编程门阵列（FPGA），以及分别耦合到可配置逻辑块的第一和第二阵列的第一和第二配置高速缓存存储器。 第一配置高速缓存存储器阵列可以存储重新配置第一阵列可配置逻辑块的值，或者作为RAM操作。 类似地，第二配置高速缓存阵列可以存储重新配置第二可配置逻辑块阵列的值，或者作为RAM操作。 独立地控制第一配置高速缓冲存储器阵列和第二配置高速缓存存储器阵列，使得可以实现FPGA的部分重新配置。 此外，第二配置高速缓存存储器阵列可以存储重新配置可配置逻辑块的第一（而不是第二）阵列的值，从而提供第二级重配置高速缓冲存储器。

公开(公告)号：US6057708A

公开(公告)日：2000-05-02

申请号：US902375

申请日：1997-07-29

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17732 ,  H03K19/17744

摘要： A user-defined logic device, such as a field programmable gate array (FPGA), having a dedicated internal bus, a plurality of dedicated bus interface circuits, and a programmable logic array. The dedicated bus interface circuits are connected in parallel to the dedicated internal bus. The programmable logic array is programmable to implement one or more functions. The programmable logic array is coupled to the dedicated bus interface circuits, such that each function is coupled to a corresponding bus interface circuit. The functions can communicate with one another through the bus interface circuits and internal bus, or through communication pathways located within the programmable logic array. In addition, the functions can communicate with devices external to the user-defined logic device through a bus bridge circuit which is coupled to the dedicated internal bus, or directly through the pins of the user-defined logic device.

摘要翻译： 用户定义的逻辑器件，例如现场可编程门阵列（FPGA），具有专用内部总线，多个专用总线接口电路和可编程逻辑阵列。 专用总线接口电路与专用内部总线并联连接。 可编程逻辑阵列可编程以实现一个或多个功能。 可编程逻辑阵列耦合到专用总线接口电路，使得每个功能耦合到相应的总线接口电路。 这些功能可以通过总线接口电路和内部总线或通过位于可编程逻辑阵列内的通信通路相互通信。 此外，功能可以通过耦合到专用内部总线或直接通过用户定义的逻辑器件引脚的总线桥式电路与用户定义的逻辑器件外部的器件通信。

公开(公告)号：US5898319A

公开(公告)日：1999-04-27

申请号：US853975

申请日：1997-05-09

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： G06F7/50 ,  G06F7/503 ,  G06F7/507 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F7/507 ,  G06F7/503 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  G06F2207/4812

摘要： A carry logic circuit for a field programmable gate array (FPGA) which allows a carry input signal to be propagated through the carry logic circuit without passing through a multiplexer of another series connected circuit element. The carry logic circuit uses a function generator of the FPGA to provide a propagate signal in response to first and second input signals provided to the carry logic circuit. Also described are methods for performing a carry logic function in an FPGA.

摘要翻译： 用于现场可编程门阵列（FPGA）的进位逻辑电路，其允许进位输入信号通过进位逻辑电路传播而不通过另一串联电路元件的多路复用器。 进位逻辑电路使用FPGA的函数发生器来响应于提供给进位逻辑电路的第一和第二输入信号来提供传播信号。 还描述了在FPGA中执行进位逻辑功能的方法。

公开(公告)号：US4809212A

公开(公告)日：1989-02-28

申请号：US747079

申请日：1985-06-19

申请人： Bernard J. New ,  Timothy J. Flaherty

发明人： Bernard J. New ,  Timothy J. Flaherty

IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/527

CPC分类号： G06F7/5324 ,  G06F2207/382 ,  G06F2207/3884

摘要： A multiplier formed as a single integrated circuit chip generates in consecutive clock cycles the single-precision partial products of multiple-precision operands. Provision of an on-chip temporary register and "wrap-back" path avoids transmitting and externally storing intermediate results so that no clock cycles are used solely for data-transfers or other "overhead". Consecutive double-precision multiplications can be performed concurrently so that complete quadruple-precision products are generated every four cycles.

摘要翻译： 形成为单个集成电路芯片的乘法器在连续的时钟周期内产生多精度操作数的单精度部分乘积。 提供片上临时寄存器和“回绕”路径避免了传输和外部存储中间结果，使得没有时钟周期仅用于数据传输或其他“开销”。 可以同时执行连续双精度乘法，以便每四个周期生成完整的四倍精度乘积。

公开(公告)号：US4393468A

公开(公告)日：1983-07-12

申请号：US247675

申请日：1981-03-26

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： G06F9/30 ,  G06F7/575 ,  G06F15/78 ,  G06F17/10 ,  G06F17/14 ,  G06F17/16 ,  G06F13/00

CPC分类号： G06F7/575 ,  G06F15/7896 ,  G06F9/30036 ,  G06F2207/3828 ,  G06F2207/3896

摘要： A programmable device for signal processing applications in which short loops of digital data are processed repetitively and in parallel. The device consist of five independently programmable subsystems whose functions are able to operate simultaneously. The apparatus is intended for use in a connection with a digital multiplier device and a digital memory device for such signal processing applications as fast Fourier transforms and time domain filtering in real time or near real time. The five parallel functions are1. to move data in and out of an external memory device between selected registers;2. to move data in and out of an external multiplier between selected registers and an arithmetic logic unit (ALU);3. to move data from the output of a multiplier to selected registers and to the ALU;4. to propagate data selectively through a chain of registers, the chain being of preselectable length; and5. to perform selected arithmetic and logic operations.The device is provided with an instruction set capable of completely defining any of the five simultaneously allowable functions. The device structure is modular to permit expansion of data word length at the ALU. Internally generated control bit signals are capable of explicitly forcing a carry or inhibiting a carry, thereby to permit independent parallel operation or extended word length operation under program control. The entire apparatus is intended to be embodied as an integrated circuit in a single chip of semiconductor material.

摘要翻译： 一种用于信号处理应用的可编程设备，其中数字数据的短循环被重复并行地处理。 该器件由五个独立可编程子系统组成，其功能能够同时工作。 该装置旨在用于与数字乘法器装置和用于诸如快速傅里叶变换和实时或近实时的时域滤波之类的信号处理应用的数字乘法器装置的连接。 五个并行功能是1.在所选择的寄存器之间移动数据进出外部存储器件; 2.选择寄存器和算术逻辑单元（ALU）之间的数据输入和输出外部乘法器; 3.将数据从乘法器的输出移动到选择的寄存器和ALU; 4.通过一组寄存器选择性地传播数据，链条是预选的长度; 和5.执行所选的算术和逻辑运算。 该装置设置有能够完全限定五个同时允许的功能中的任何一个的指令集。 器件结构是模块化的，允许在ALU扩展数据字长度。 内部产生的控制位信号能够明确地强制进位或禁止进位，从而允许在程序控制下独立的并行操作或扩展的字长度操作。 整个装置旨在被实现为半导体材料的单个芯片中的集成电路。

公开(公告)号：US08399983B1

公开(公告)日：2013-03-19

申请号：US12332505

申请日：2008-12-11

申请人： Bernard J. New

发明人： Bernard J. New

IPC分类号： H01L23/04

CPC分类号： H01L25/18 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A semiconductor assembly with an integrated circuit (IC) and a companion device. An exemplary semiconductor assembly includes a printed circuit board (PCB) and first and second ICs. The PCB has first contacts on a top surface and second contacts on a bottom surface. The first contacts are vertically aligned with the second contacts and are electrically coupled by vias in the PCB. The first IC has first terminals respectively coupled to the first contacts of the PCB, the first terminals including first input/output (IO) terminals. The second IC includes at least one die, and second terminals coupled to at least a portion of the second contacts of the PCB. The second terminals include second IO terminals of the companion die, and are respectively coupled to those of the second contacts that are vertically aligned with those of the first contacts respectively coupled to the first IO terminals.

摘要翻译： 具有集成电路（IC）和配套装置的半导体组件。 示例性的半导体组件包括印刷电路板（PCB）和第一和第二IC。 PCB在顶表面上具有第一触点，在底表面上具有第二触点。 第一触点与第二触点垂直对准并且通过PCB中的通孔电耦合。 第一IC具有分别耦合到PCB的第一触点的第一端子，第一端子包括第一输入/输出端子。 第二IC包括至少一个管芯，以及耦合到PCB的第二接触件的至少一部分的第二端子。 第二端子包括配对管芯的第二IO端子，并且分别耦合到与分别耦合到第一IO端子的第一触头的垂直对准的第二触点的端子。

公开(公告)号：US07971072B1

公开(公告)日：2011-06-28

申请号：US11077052

申请日：2005-03-10

申请人： Adam P. Donlin ,  Prasanna Sundararajan ,  Bernard J. New

发明人： Adam P. Donlin ,  Prasanna Sundararajan ,  Bernard J. New

IPC分类号： G06F12/14 ,  H04L9/32 ,  H04L9/00

CPC分类号： H04L63/0428 ,  G06F17/5054 ,  G06F21/76 ,  G06F2217/66 ,  H04L9/14 ,  H04L9/3271 ,  H04L63/10

摘要： A method and system are disclosed. The system includes a trusted loader. The method includes downloading an IP core from a vendor to a target device. The IP core is received in an encrypted form at the target device, which can be, for example, a programmable logic device.

摘要翻译： 公开了一种方法和系统。 该系统包括可信任的加载程序。 该方法包括将IP核从供应商下载到目标设备。 在目标设备处以加密形式接收IP内核，其可以是例如可编程逻辑设备。