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    Programmable logic device including configuration data or user data memory slices
    42.
    发明授权
    Programmable logic device including configuration data or user data memory slices 失效

    公开(公告)号：US5784313A

    公开(公告)日：1998-07-21

    申请号：US516808

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G06F17/50 ,  G11C5/00 ,  H03K19/177 ,  G11C13/00

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

    Applications of cascading DSP slices
    45.
    发明授权
    Applications of cascading DSP slices 有权
    级联DSP片的应用

    公开(公告)号：US07567997B2

    公开(公告)日：2009-07-28

    申请号：US11019518

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/48

    CPC分类号： G06F7/5443

    摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

    摘要翻译： 在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。 该IC允许实现一些基本的数学函数，例如加，减，乘和除。 可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

    Tissue extraction device and method of using the same
    47.
    发明申请
    Tissue extraction device and method of using the same 审中-公开
    组织提取装置及其使用方法

    公开(公告)号：US20080058674A1

    公开(公告)日：2008-03-06

    申请号：US11511531

    申请日：2006-08-29

    申请人： Lex Jansen ,  Art Ferdinand ,  Hugues F. Malandain ,  Claudia Orellana ,  Chris Phan ,  Derek Rothwell ,  Jennifer Wong

    发明人： Lex Jansen ,  Art Ferdinand ,  Hugues F. Malandain ,  Claudia Orellana ,  Chris Phan ,  Derek Rothwell ,  Jennifer Wong

    IPC分类号： A61B10/00

    CPC分类号： A61B10/0266 ,  A61B10/025 ,  A61B10/04 ,  A61B2017/00867

    摘要： Apparatuses and methods for performing minimally invasive medical procedures are disclosed herein. In one example, an apparatus includes an elongate body that has a deformable distal portion and defines a lumen, the lumen extends through the deformable distal portion. The deformable distal portion has a cutting portion and defines an opening. The elongate body has a first configuration in which the opening is a first size and a second configuration in which the opening is a second size smaller than the first size of the opening. The elongate body in the first configuration is configured to be percutaneously inserted at least partially into a tissue such that at least a portion of the tissue is disposed within the lumen. The elongate body is configured to move to the second configuration when the elongate body reaches a threshold temperature while inserted in the tissue.

    摘要翻译： 本文公开了用于执行微创医疗程序的装置和方法。 在一个示例中，设备包括具有可变形的远侧部分并限定内腔的细长主体，内腔延伸穿过可变形远端部分。 可变形远端部分具有切割部分并限定开口。 细长体具有第一构造，其中开口是第一尺寸和第二构造，其中开口是小于开口的第一尺寸的第二尺寸。 第一构造中的细长体构造成至少部分地经皮地插入到组织中，使得组织的至少一部分设置在内腔内。 细长体构造成当细长体在插入组织中时达到阈值温度时移动到第二构型。

    Self-repairing redundancy for memory blocks in programmable logic devices
    48.
    发明授权
    Self-repairing redundancy for memory blocks in programmable logic devices 有权
    可编程逻辑器件中的存储器块的自修复冗余

    公开(公告)号：US07216277B1

    公开(公告)日：2007-05-08

    申请号：US10717040

    申请日：2003-11-18

    申请人： Tony K. Ngai ,  Jennifer Wong ,  Wayson J. Lowe

    发明人： Tony K. Ngai ,  Jennifer Wong ,  Wayson J. Lowe

    IPC分类号： G01R31/28 ,  G11C29/00

    CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/846

    摘要： Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.

    摘要翻译： 可编程逻辑器件（PLD），包括自修复RAM电路，以及自动替换RAM阵列中有缺陷的列的方法。 包括冗余列的RAM电路在PLD配置顺序期间使用内置的自检（BIST）过程进行测试。 如果检测到有缺陷的列，则错误标志被存储在相关联的易失性存储器电路中。 BIST程序完成后，PLD配置过程继续。 错误标志的存在导致配置数据绕过故障列，并直接传递到替换列。 配置过程继续，直到电路的其余部分被配置，包括冗余列。 在其他实施例中，独立于PLD配置过程启动BIST过程。 当检测到有缺陷的列时，以对用户透明的方式，将数据从有缺陷的列分流到冗余列的用户操作恢复。

    Method and apparatus for discriminating against signal interference
    50.
    发明授权
    Method and apparatus for discriminating against signal interference 有权
    用于区分信号干扰的方法和装置

    公开(公告)号：US06353341B1

    公开(公告)日：2002-03-05

    申请号：US09439844

    申请日：1999-11-12

    申请人： Austin H. Lesea ,  Peter H. Alfke ,  Jennifer Wong ,  Steven P. Young

    发明人： Austin H. Lesea ,  Peter H. Alfke ,  Jennifer Wong ,  Steven P. Young

    IPC分类号： G01R2902

    CPC分类号： G01R31/31922 ,  G01R31/31937

    摘要： A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

    摘要翻译： 监视时钟信号以检测从第一逻辑状态到第二逻辑状态的转变。 一旦检测到该转变，则在时间信号的后续转换在信号干扰最显着的预定时间段期间被忽略。 在经过预定时间段之后，再次监视时钟信号以检测随后的状态转换。 在一些实施例中，使用延迟电路来延迟时钟信号以产生延迟的时钟信号，该延迟时钟信号用于将时钟信号强制到第二逻辑状态达预定时间段。 在一个实施例中，通过延迟电路上的一个或多个可选择的抽头，预定时间段是用户可选择的。