公开(公告)号：US08839356B2

公开(公告)日：2014-09-16

申请号：US12006150

申请日：2007-12-31

Applicant: Michael A. Rothman ,  Arvind Kumar ,  Vincent J. Zimmer ,  Patrick G. Kutch ,  Omer Levy

Inventor： Michael A. Rothman ,  Arvind Kumar ,  Vincent J. Zimmer ,  Patrick G. Kutch ,  Omer Levy

IPC: G06F1/00 ,  G06F7/04 ,  G06F17/30 ,  H04L9/32 ,  H04L29/06 ,  G06F21/85

CPC classification number: H04L63/08 ,  G06F1/3209 ,  G06F21/85 ,  H04L12/12 ,  H04L63/083 ,  Y02D50/40

Abstract: Methods, apparatuses, and computer program products that respond to wake events of communication networks are disclosed. One or more embodiments comprise setting a wake password of a computing device, such as a notebook computer or a server. Some of the embodiments comprise receiving a wake request from a communications network, establishing a secure communication session, and setting the wake password with the secure communication session. Some embodiments comprise an apparatus having a network controller to allow a platform to communicate via a communications network, non-volatile memory that stores a wake password, and a management controller that may communicate with a management console via a secure communication session to update the wake password. One or more embodiments the network controller may wake management hardware and/or wake the management controller while keeping one or more of the devices in the power conservation mode.

Abstract translation: 公开了响应通信网络的唤醒事件的方法，设备和计算机程序产品。 一个或多个实施例包括设置诸如笔记本计算机或服务器之类的计算设备的唤醒密码。 一些实施例包括从通信网络接收唤醒请求，建立安全通信会话，以及利用安全通信会话设置唤醒密码。 一些实施例包括具有网络控制器的设备，其允许平台经由通信网络进行通信，存储唤醒密码的非易失性存储器以及可以经由安全通信会话与管理控制台通信以更新唤醒的管理控制器 密码。 一个或多个实施例，网络控制器可以在保持一个或多个设备处于功率节省模式的同时唤醒管理硬件和/或唤醒管理控制器。

公开(公告)号：US08680623B2

公开(公告)日：2014-03-25

申请号：US13433815

申请日：2012-03-29

Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC: H01L21/8244 ,  H01L21/70

CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US20130344677A1

公开(公告)日：2013-12-26

申请号：US13531780

申请日：2012-06-25

Applicant: Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC: H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

公开(公告)号：US20130341754A1

公开(公告)日：2013-12-26

申请号：US13531654

申请日：2012-06-25

Applicant: Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

公开(公告)号：US08482075B2

公开(公告)日：2013-07-09

申请号：US13468270

申请日：2012-05-10

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert Robison

IPC: H01L21/70

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US08343781B2

公开(公告)日：2013-01-01

申请号：US12886612

申请日：2010-09-21

Applicant: Arvind Kumar ,  Anthony I-Chih Chou ,  Shreesh Narasimha

Inventor： Arvind Kumar ,  Anthony I-Chih Chou ,  Shreesh Narasimha

IPC: G01R31/26 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.

Abstract translation: 公开了一种用于电气掩模检查的装置和方法。 在两个金属层和通孔层之间形成扫描链。 三层之一是被测功能层，另外两层是测试层。 使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。

公开(公告)号：US20120192000A1

公开(公告)日：2012-07-26

申请号：US13436835

申请日：2012-03-30

Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

IPC: G06F1/00

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

公开(公告)号：US20120068174A1

公开(公告)日：2012-03-22

申请号：US12886612

申请日：2010-09-21

Applicant: Arvind Kumar ,  Anthony I-Chih Chou ,  Shreesh Narasimha

Inventor： Arvind Kumar ,  Anthony I-Chih Chou ,  Shreesh Narasimha

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.

Abstract translation: 公开了一种用于电气掩模检查的装置和方法。 在两个金属层和通孔层之间形成扫描链。 三层之一是被测功能层，另外两层是测试层。 使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。

公开(公告)号：US08034692B2

公开(公告)日：2011-10-11

申请号：US12581924

申请日：2009-10-20

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US07936042B2

公开(公告)日：2011-05-03

申请号：US11939017

申请日：2007-11-13

Applicant: Arvind Kumar

Inventor： Arvind Kumar

IPC: H01L29/02

CPC classification number: H01L21/26586 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.

Abstract translation: 提供了包括硅含量体的场效应晶体管。 在形成栅极电介质，栅极电极和第一栅极间隔物之后，形成漏极侧沟槽并填充宽带隙半导体材料。 可选地，可以形成源极沟槽并填充硅锗合金以增强场效应晶体管的导通电流。 进行光晕注入和源极和漏极离子注入以形成各种掺杂区域。 由于宽带隙半导体材料作为比硅的带隙宽的带隙，由于在漏极中使用宽带隙半导体材料，因此冲击电离降低，因此，场效应晶体管的击穿电压比较 涉及在漏极区域中使用硅的晶体管。