中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

156 records (took 0.043 seconds)

    High speed display interface
    41.
    发明授权
    High speed display interface 有权

    公开(公告)号：US09953613B2

    公开(公告)日：2018-04-24

    申请号：US14661723

    申请日：2015-03-18

    Applicant: APPLE INC.

    Inventor： Paolo Sacchetto ,  David W. Lum ,  Christopher P. Tann ,  Guy Cote ,  Chaohao Wang ,  Sandro H. Pintz

    IPC: G09G5/00

    CPC classification number: G09G5/006 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2340/0435 ,  G09G2350/00 ,  G09G2370/10

    Abstract: Methods and devices employing circuitry for dynamically adjusting bandwidth control of a display interface are provided. The display interface or image content is dynamically adjusted to support both high-speed image data (e.g., 120 Hz image data) and lower-speed content (e.g., 60 Hz content). For example, in some embodiments, additional pixel pipelines and/or processing lanes may be activated during the rendering of high-speed image data, but not during the rendering of low-speed image data. Additionally or alternatively, high-speed image data, but not low-speed data, may be compressed to render high-speed content over an interface that supports only low-speed content.

    Sub-pixel layout compensation
    42.
    发明授权
    Sub-pixel layout compensation 有权

    公开(公告)号：US09672765B2

    公开(公告)日：2017-06-06

    申请号：US14871894

    申请日：2015-09-30

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Mahesh B. Chappalli

    IPC: G09G5/10 ,  G09G3/20

    CPC classification number: G09G3/20 ,  G09G2300/0452 ,  G09G2320/0242 ,  G09G2320/0285 ,  G09G2320/066 ,  G09G2340/0457

    Abstract: Devices and methods for reducing or eliminating sub-pixel layout artifacts on an electronic display are provided. One such device may include an electronic display to display image data, a processor to generate the image data, and sub-pixel layout compensation circuitry that modifies the image data to reduce or eliminate a sub-pixel layout artifact of the electronic display by modifying pixels of the image data on a sub-pixel-by-sub-pixel basis. The sub-pixel layout compensation circuitry may adjust a sub-pixel of a first color in a first pixel based at least in part on a first gradient between the sub-pixel of the first color of the first pixel and a sub-pixel of the first color of a second pixel.

    Neighbor context caching in block processing pipelines
    43.
    发明授权
    Neighbor context caching in block processing pipelines 有权
    块处理管道中的邻居上下文缓存

    公开(公告)号：US09305325B2

    公开(公告)日：2016-04-05

    申请号：US14037313

    申请日：2013-09-25

    Applicant: Apple Inc.

    Inventor： Joseph J. Cheng ,  Guy Cote ,  Marc A. Schaub ,  Jim C. Chou

    IPC: G06T1/20 ,  G06T1/60 ,  H04N19/61 ,  H04N19/423 ,  H04N19/436

    CPC classification number: G06T1/20 ,  G06T1/60 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61

    Abstract: Methods and apparatus for caching neighbor data in a block processing pipeline that processes blocks in knight's order with quadrow constraints. Stages of the pipeline may maintain two local buffers that contain data from neighbor blocks of a current block. A first buffer contains data from the last C blocks processed at the stage. A second buffer contains data from neighbor blocks on the last row of a previous quadrow. Data for blocks on the bottom row of a quadrow are stored to an external memory at the end of the pipeline. When a block on the top row of a quadrow is input to the pipeline, neighbor data from the bottom row of the previous quadrow is read from the external memory and passed down the pipeline, each stage storing the data in its second buffer and using the neighbor data in the second buffer when processing the block.

    Abstract translation: 用于在块处理管道中缓存邻居数据的方法和装置，其以四限制约束以骑士顺序处理块。 管道的阶段可以维护两个包含当前块的相邻块的数据的本地缓冲器。 第一个缓冲区包含在该阶段处理的最后一个C块的数据。 第二个缓冲区包含来自前一个四边形最后一行的相邻块的数据。 四边形底行中的块的数据存储在流水线末端的外部存储器中。 当四边形的顶行上的块被输入到流水线时，从外部存储器读取来自前一个四边形的底行的邻居数据，并将其传送到流水线，每个级将数据存储在其第二缓冲器中，并使用 处理块时第二个缓冲区中的邻居数据。

    Reference frame data prefetching in block processing pipelines
    44.
    发明授权
    Reference frame data prefetching in block processing pipelines 有权
    在块处理流水线中预取参考帧数据

    公开(公告)号：US09292899B2

    公开(公告)日：2016-03-22

    申请号：US14037318

    申请日：2013-09-25

    Applicant: Apple Inc.

    Inventor： Marc A. Schaub ,  Joseph J. Cheng ,  Mark P. Rygh ,  Guy Cote

    IPC: G06F13/00 ,  G06T1/20 ,  G06T1/60 ,  H04N19/61 ,  H04N19/423 ,  H04N19/436

    CPC classification number: G06T1/20 ,  G06T1/60 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61

    Abstract: Block processing pipeline methods and apparatus in which pixel data from a reference frame is prefetched into a search window memory. The search window may include two or more overlapping regions of pixels from the reference frame corresponding to blocks from the rows in the input frame that are currently being processed in the pipeline. Thus, the pipeline may process blocks from multiple rows of an input frame using one set of pixel data from a reference frame that is stored in a shared search window memory. The search window may be advanced by one column of blocks by initiating a prefetch for a next column of reference data from a memory. The pipeline may also include a reference data cache that may be used to cache a portion of a reference frame and from which at least a portion of a prefetch for the search window may be satisfied.

    Abstract translation: 块处理流水线方法和装置，其中来自参考帧的像素数据被预取到搜索窗口存储器中。 搜索窗口可以包括对应于当前正在流水线处理的输入帧中的行的来自参考帧的两个或更多个重叠区域的像素。 因此，流水线可以使用来自存储在共享搜索窗口存储器中的参考帧的一组像素数据来处理来自输入帧的多行的块。 搜索窗口可以由一列块提前，通过从存储器发起下一列参考数据的预取。 流水线还可以包括可用于缓存参考帧的一部分的参考数据高速缓存，并且可以从该参考数据高速缓冲存储器可以满足搜索窗口的预取的至少一部分。

    CHROMA CACHE ARCHITECTURE IN BLOCK PROCESSING PIPELINES
    45.
    发明申请
    CHROMA CACHE ARCHITECTURE IN BLOCK PROCESSING PIPELINES 有权
    块式加工管道中的色谱高速缓存架构

    公开(公告)号：US20160065973A1

    公开(公告)日：2016-03-03

    申请号：US14472119

    申请日：2014-08-28

    Applicant: APPLE INC.

    Inventor： Guy Cote ,  Joseph P. Bratt ,  Timothy J. Millet ,  Shing I. Kong ,  Joseph J. Cheng

    IPC: H04N19/186 ,  H04N19/423 ,  H04N19/172 ,  H04N19/176

    CPC classification number: H04N19/186 ,  G06F12/00 ,  G06F12/0207 ,  G06F12/0862 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/455 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06T1/60 ,  H04N19/127 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/433 ,  H04N19/439

    Abstract: Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.

    Abstract translation: 在块处理流水线中缓存参考数据的方法和装置。 可以实现缓存，其可以从存储器预取哪个对应于在流水线中处理的块的运动矢量的参考数据。 可以在处理阶段之前一个或多个阶段启动用于运动矢量的预取。 高速缓存的缓存标签可以由运动向量定义。 当接收到运动矢量时，可以检查标签以确定是否存在与缓存中的向量（高速缓存命中）相对应的高速缓存块。 在缓存未命中时，根据替换策略来选择高速缓存中的高速缓存块，相应的标签被更新，并且发出用于各个参考数据的预取（例如，经由DMA）。

    Delayed chroma processing in block processing pipelines
    46.
    发明授权
    Delayed chroma processing in block processing pipelines 有权
    在块处理管道中延迟色度处理

    公开(公告)号：US09270999B2

    公开(公告)日：2016-02-23

    申请号：US14037310

    申请日：2013-09-25

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Craig M. Okruhlica

    IPC: H04N19/86 ,  H04N19/107 ,  H04N19/42 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/436

    CPC classification number: H04N19/186 ,  H04N19/107 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176 ,  H04N19/182 ,  H04N19/40 ,  H04N19/423 ,  H04N19/436 ,  H04N19/439 ,  H04N19/52 ,  H04N19/593 ,  H04N19/86 ,  H04N19/96

    Abstract: A block processing pipeline in which macroblocks are input to and processed according to row groups so that adjacent macroblocks on a row are not concurrently at adjacent stages of the pipeline. The input method may allow chroma processing to be postponed until after luma processing. One or more upstream stages of the pipeline may process luma elements of each macroblock to generate luma results such as a best mode for processing the luma elements. Luma results may be provided to one or more downstream stages of the pipeline that process chroma elements of each macroblock. The luma results may be used to determine processing of the chroma elements. For example, if the best mode for luma is an intra-frame mode, then a chroma processing stage may determine a best intra-frame mode for chroma and reconstruct the chroma elements according to the best chroma intra-frame mode.

    Abstract translation: 块处理流水线，其中宏块被输入到并根据行组进行处理，使得一行上的相邻宏块不是在流水线的相邻阶段同时进行。 输入法可以允许色度处理被推迟直到亮度处理。 流水线的一个或多个上游级可以处理每个宏块的亮度元素以产生亮度结果，例如用于处理亮度元素的最佳模式。 亮度结果可以被提供给处理每个宏块的色度元素的流水线的一个或多个下游阶段。 亮度结果可用于确定色度元素的处理。 例如，如果亮度的最佳模式是帧内模式，则色度处理阶段可以确定用于色度的最佳帧内模式，并且根据最佳色度帧内模式重建色度元素。

    SYSTEMS AND METHODS FOR LOCAL TONE MAPPING
    47.
    发明申请
    SYSTEMS AND METHODS FOR LOCAL TONE MAPPING 有权
    用于局部色调映射的系统和方法

    公开(公告)号：US20150348246A1

    公开(公告)日：2015-12-03

    申请号：US14822316

    申请日：2015-08-10

    Applicant: APPLE INC.

    Inventor： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

    IPC: G06T5/00 ,  G06T1/20 ,  G06K9/38 ,  G06T5/50

    CPC classification number: G06T5/001 ,  G06K9/38 ,  G06T1/20 ,  G06T5/002 ,  G06T5/003 ,  G06T5/008 ,  G06T5/50 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20028 ,  G06T2207/20208

    Abstract: Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.

    Abstract translation: 提供了本地色调映射的系统和方法。 在一个示例中，电子设备包括电子显示器，成像设备和图像信号处理器。 电子显示器可以显示第一位深度的图像，并且成像装置可以包括获得比第一位深度更高的位深度的图像数据的图像传感器。 图像信号处理器可以处理图像数据，并且可以包括本地色调映射逻辑，其可以将空间上变化的本地色调曲线应用于图像数据的像素，以便在显示器上显示时保持局部对比度。 本地色调映射逻辑可以平滑应用于像素和另一附近像素之间的强度差超过阈值的局部色调曲线。

    PARALLEL HARDWARE AND SOFTWARE BLOCK PROCESSING PIPELINES
    49.
    发明申请
    PARALLEL HARDWARE AND SOFTWARE BLOCK PROCESSING PIPELINES 有权
    并行硬件和软件块处理管道

    公开(公告)号：US20150092854A1

    公开(公告)日：2015-04-02

    申请号：US14039729

    申请日：2013-09-27

    Applicant: Apple Inc.

    Inventor： James E. Orr ,  Timothy John Millet ,  Joseph J. Cheng ,  Nitin Bhargava ,  Guy Cote

    IPC: H04N19/436 ,  H04N19/433 ,  H04N19/51 ,  H04N19/583 ,  H04N19/43

    CPC classification number: H04N19/43 ,  G06T1/20 ,  H04N19/433 ,  H04N19/436 ,  H04N19/51 ,  H04N19/513

    Abstract: A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.

    Abstract translation: 一个块处理流水线，包括一个软件流水线和并行运行的硬件流水线。 软件管道在硬件管道之前至少运行一个程序段。 流水线的各个阶段可以各自包括在该阶段对当前块执行一个或多个操作的硬件流水线组件。 管道的至少一个阶段还可以包括软件流水线组件，该软件流水线组件在硬件组件正在处理当前块时，在流水线阶段确定用于处理下一个块的硬件组件的配置。 软件管线组件可以根据从流水线的上游级获得的与下一块相关的信息来确定配置。 软件管道组件还可以获得并使用与先前在该阶段处理的块相关的信息。

    DATA STORAGE AND ACCESS IN BLOCK PROCESSING PIPELINES
    50.
    发明申请
    DATA STORAGE AND ACCESS IN BLOCK PROCESSING PIPELINES 有权
    数据存储和访问块处理管道

    公开(公告)号：US20150092843A1

    公开(公告)日：2015-04-02

    申请号：US14039764

    申请日：2013-09-27

    Applicant: Apple Inc.

    Inventor： Timothy John Millet ,  Mark P. Rygh ,  Craig M. Okruhlica ,  Jim C. Chou ,  Guy Cote ,  Gaurav S. Gulati ,  Joseph J. Cheng ,  Joseph P. Bratt

    IPC: H04N19/57 ,  H04N19/186 ,  H04N19/182

    CPC classification number: H04N19/423 ,  H04N19/53

    Abstract: Block processing pipeline methods and apparatus in which reference data are stored to a memory according to tile formats to reduce memory accesses when fetching the data from the memory. When the pipeline stores reference data from a current frame being processed to memory as a reference frame, the reference samples are stored in macroblock sequential order. Each macroblock sample set is stored as a tile. Reference data may be stored in tile formats for luma and chroma. Chroma reference data may be stored in tile formats for chroma 4:2:0, 4:2:2, and/or 4:4:4 formats. A stage of the pipeline may write luma and chroma reference data for macroblocks to memory according to one or more of the macroblock tile formats in a modified knight's order. The stage may delay writing the reference data from the macroblocks until the macroblocks have been fully processed by the pipeline.

    Abstract translation: 块处理管道方法和装置，其中参考数据根据瓦片格式存储到存储器中，以在从存储器取出数据时减少存储器访问。 当流水线将正在处理的当前帧的参考数据存储为参考帧时，参考样本以宏块顺序存储。 每个宏块样本集被存储为一个图块。 参考数据可以以瓦片和色度的瓦片格式存储。 色度参考数据可以以瓦4：2：0,4：2：2和/或4：4：4格式的瓦片格式存储。 流水线的一个阶段可以根据改进的骑士顺序中的一个或多个宏块瓦片格式将宏块的亮度和色度参考数据写入存储器。 该阶段可以延迟从宏块写入参考数据，直到宏块已被管道完全处理。

Patent Agency Ranking