公开(公告)号：US20120061743A1

公开(公告)日：2012-03-15

申请号：US13004229

申请日：2011-01-11

申请人： Nobutaka WATANABE ,  Kazuyuki Higashi ,  Gaku Sudo

发明人： Nobutaka WATANABE ,  Kazuyuki Higashi ,  Gaku Sudo

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.

摘要翻译： 根据一个实施例，半导体存储器件包括层叠体，接触部，半导体部件，电荷存储层和穿透部件。 层叠体包括与绝缘膜交替堆叠的电极膜。 层叠体的端部的结构是具有设置在每个电极膜上的台阶的台阶构造。 触点从端部的上方连接到电极膜。 半导体构件设置在除了端部之外的层叠体的一部分中，以在层叠方向上刺穿层叠体。 电荷存储层设置在电极膜和半导体部件之间。 穿透构件在层叠方向上刺穿端部。 穿透构件不包含与电荷存储层相同的材料。

公开(公告)号：US07737737B2

公开(公告)日：2010-06-15

申请号：US12128106

申请日：2008-05-28

申请人： Kazuyuki Higashi ,  Shinsuke Yonetani

发明人： Kazuyuki Higashi ,  Shinsuke Yonetani

IPC分类号： H03K3/00

CPC分类号： H03K17/0406 ,  H03K17/04123 ,  H03K17/163 ,  H03K17/168

摘要： A drive circuit for driving a voltage-driven-type element including a gate terminal, an emitter terminal and a collector terminal includes a first semiconductor switch including an output terminal disposed between a power source for the drive circuit and the gate terminal, a first resistor disposed between the output terminal and the gate terminal and a capacitive element connected in parallel with the first semiconductor switch. The capacitive element supplies an external electric charge from the power source to a portion between the gate terminal and the emitter terminal after an internal electric charge accumulated in the portion between the gate terminal and the emitter terminal is supplied to a portion between the gate terminal and the collector terminal.

摘要翻译： 用于驱动包括栅极端子，发射极端子和集电极端子的电压驱动型元件的驱动电路包括：第一半导体开关，包括设置在用于驱动电路的电源和栅极端子之间的输出端子;第一电阻器 设置在输出端子和栅极端子之间以及与第一半导体开关并联连接的电容元件。 在将栅极端子和发射极端子之间的部分积蓄的内部电荷供给到栅极端子与发射极端子之间的部分之后，电容元件将电源从外部电荷提供给栅极端子与发射极端子之间的部分， 集电极端子。

公开(公告)号：US07514967B2

公开(公告)日：2009-04-07

申请号：US11601313

申请日：2006-11-17

申请人： Kazuyuki Higashi ,  Yoshinori Sato

发明人： Kazuyuki Higashi ,  Yoshinori Sato

IPC分类号： H03B1/00

CPC分类号： H03K17/0828 ,  H03K17/166 ,  H03K17/168 ,  H03K17/28 ,  H03K17/567

摘要： A driver apparatus and method for driving a voltage driven type switching element that discharge an electrical charge stored at the gate terminal of the voltage driven type switching element at a discharge rate. The discharge rate is controlled so that the change rate over time of the voltage between the collector and emitter terminals of the voltage driven type switching element is limited to a second change rate during the turn-off operation. The starting time of the control of the change rate over time to attain the second change rate is delayed for a predetermined delay time after start of the turn-off operation and before a time when the voltage between the collector and emitter terminals first reaches the power source voltage level. During the delay time, the discharge rate is initially at a first change rate higher than the second change rate.

摘要翻译： 一种用于驱动电压驱动型开关元件的驱动器装置和方法，其以放电速率放电存储在电压驱动型开关元件的栅极端子处的电荷。 控制放电率，使得电压驱动型开关元件的集电极和发射极端子之间的电压随时间的变化率在关断操作期间被限制为第二变化率。 随着时间的推移控制变化率以达到第二变化率的开始时间在关断操作开始之后延迟预定的延迟时间，并且在集电极和发射极端子之间的电压首先达到功率 源电压电平。 在延迟时间期间，放电速率最初处于高于第二变化率的第一变化率。

公开(公告)号：US20080303560A1

公开(公告)日：2008-12-11

申请号：US12128106

申请日：2008-05-28

申请人： Kazuyuki Higashi ,  Shinsuke Yonetani

发明人： Kazuyuki Higashi ,  Shinsuke Yonetani

IPC分类号： H03K3/00

CPC分类号： H03K17/0406 ,  H03K17/04123 ,  H03K17/163 ,  H03K17/168

摘要： A drive circuit for driving a voltage-driven-type element including a gate terminal, an emitter terminal and a collector terminal includes a first semiconductor switch including an output terminal disposed between a power source for the drive circuit and the gate terminal, a first resistor disposed between the output terminal and the gate terminal and a capacitive element connected in parallel with the first semiconductor switch. The capacitive element supplies an external electric charge from the power source to a portion between the gate terminal and the emitter terminal after an internal electric charge accumulated in the portion between the gate terminal and the emitter terminal is supplied to a portion between the gate terminal and the collector terminal.

摘要翻译： 用于驱动包括栅极端子，发射极端子和集电极端子的电压驱动型元件的驱动电路包括：第一半导体开关，包括设置在用于驱动电路的电源和栅极端子之间的输出端子;第一电阻器 设置在输出端子和栅极端子之间以及与第一半导体开关并联连接的电容元件。 在将栅极端子和发射极端子之间的部分积蓄的内部电荷供给到栅极端子与发射极端子之间的部分之后，电容元件将电源从外部电荷提供给栅极端子与发射极端子之间的部分， 集电极端子。

公开(公告)号：US20070158849A1

公开(公告)日：2007-07-12

申请号：US11619338

申请日：2007-01-03

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga

IPC分类号： H01L23/52

CPC分类号： G06F17/5068 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to an embodiment of the present invention has: a semiconductor substrate; an interlayer insulating film formed above the semiconductor substrate; a protective film formed on the interlayer insulating film, the protective film having a higher density than that of the interlayer insulating film; at least one of a wiring and a dummy wiring formed in the interlayer insulating film and the protective film; and a separation wall formed within the interlayer insulating film so as to surround a low density region to separate the low density region from other regions, a sum of covering densities of the wiring and the dummy wiring being lower than a predetermined prescribed value in the low density region.

摘要翻译： 根据本发明的实施例的半导体器件具有：半导体衬底; 形成在半导体衬底上的层间绝缘膜; 形成在所述层间绝缘膜上的保护膜，所述保护膜的密度高于所述层间绝缘膜的密度; 在层间绝缘膜和保护膜中形成的布线和虚拟布线中的至少一个; 以及形成在层间绝缘膜内的隔离壁，以便围绕低密度区域以将低密度区域与其他区域分离，布线和虚拟布线的覆盖密度之和低于低于预定的规定值 密度区域。

公开(公告)号：US07129175B2

公开(公告)日：2006-10-31

申请号：US10726678

申请日：2003-12-04

申请人： Hideshi Miyajima ,  Kazuyuki Higashi ,  Keiji Fujita ,  Toshiaki Hasegawa ,  Kiyotaka Tabuchi

发明人： Hideshi Miyajima ,  Kazuyuki Higashi ,  Keiji Fujita ,  Toshiaki Hasegawa ,  Kiyotaka Tabuchi

IPC分类号： H01L21/302 ,  H01L21/31 ,  H01L21/311

CPC分类号： H01L21/02312 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0231 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826

摘要： A semiconductor device manufacturing method comprises forming a first insulating film including silicon, carbon, nitrogen, and hydrogen above a substrate in a first chamber, carrying the substrate into a second chamber other than the first chamber, and discharging a rare gas in the second chamber, and forming a second insulating film including silicon, carbon, oxygen, and hydrogen above the first insulating film after the discharging the rare gas.

摘要翻译： 半导体器件制造方法包括在第一室中在衬底上形成包括硅，碳，氮和氢的第一绝缘膜，将衬底运送到除了第一室之外的第二室中，并且在第二室中排出稀有气体 并且在排出稀有气体之后，在第一绝缘膜上形成包括硅，碳，氧和氢的第二绝缘膜。

公开(公告)号：US07026715B2

公开(公告)日：2006-04-11

申请号：US10628689

申请日：2003-07-28

申请人： Noriaki Matsunaga ,  Kazuyuki Higashi

发明人： Noriaki Matsunaga ,  Kazuyuki Higashi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76802 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed, which comprises a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, the interlayer insulating film comprising a first insulating film and a second insulating film formed on the first insulating film, the first insulating film comprising a silicon oxide film containing carbon of a concentration, the second insulating film comprising a silicon oxide film containing carbon of a concentration lower than the concentration of the first insulating film or comprising a silicon oxide film containing substantially no carbon, a via contact made of a metal material embedded in a via hole formed in the interlayer insulating film, a diameter of the via hole in the first insulating film being smaller than that in the second insulating film at an interface between the first insulating film and the second insulating film.

摘要翻译： 公开了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的层间绝缘膜，所述层间绝缘膜包括第一绝缘膜和形成在所述第一绝缘膜上的第二绝缘膜，所述第一绝缘膜包括硅 含有浓度为碳的氧化膜，所述第二绝缘膜包含含有浓度低于所述第一绝缘膜的浓度的碳的氧化硅膜，或包含基本上不含碳的氧化硅膜，由金属材料制成的通孔接点 嵌入在所述层间绝缘膜中形成的通路孔中，所述第一绝缘膜中的所述通孔的直径小于所述第一绝缘膜和所述第二绝缘膜之间的界面处的所述第二绝缘膜中的通孔的直径。

公开(公告)号：US20050285229A1

公开(公告)日：2005-12-29

申请号：US11117726

申请日：2005-04-29

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga

IPC分类号： H01L21/288 ,  H01L21/46 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L21/76877 ,  H01L21/2885 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to an embodiment of the present invention includes a plurality of chip regions and a plurality of chip rings. The plurality of chip regions include semiconductor integrated circuits each having a multilayered wiring structure using a metal wiring, and are formed into independent chips. The plurality of chip rings has the multilayered wiring structure using the metal wiring, and surround the respective chip regions. The plurality of chip rings are electrically connected to one another.

摘要翻译： 根据本发明实施例的半导体器件包括多个芯片区域和多个芯片环。 多个芯片区域包括各自具有使用金属布线的多层布线结构的半导体集成电路，并且形成为独立的芯片。 多个芯片环具有使用金属布线的多层布线结构，并且包围各个芯片区域。 多个芯片环彼此电连接。

公开(公告)号：US06555925B1

公开(公告)日：2003-04-29

申请号：US09517187

申请日：2000-03-02

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tamao Takase ,  Hisashi Kaneko ,  Hideki Shibata

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tamao Takase ,  Hisashi Kaneko ,  Hideki Shibata

IPC分类号： H01L23544

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a lithographic process is formed of a wiring material which is copper or includes copper as a main component, and the alignment mark is formed entirely in an area outside an area where dicing is to be executed.

摘要翻译： 本发明是一种制造半导体器件的方法，其中在光刻工艺的曝光处理中使用的至少一个对准标记由铜或者铜作为主要成分的布线材料形成，并且对准标记 完全在要执行切割的区域外的区域中形成。

公开(公告)号：US08680604B2

公开(公告)日：2014-03-25

申请号：US12706195

申请日：2010-02-16

申请人： Kazuyuki Higashi ,  Tsuneo Uenaka

发明人： Kazuyuki Higashi ,  Tsuneo Uenaka

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/11582

摘要： A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.

摘要翻译： 第一区域包括：包括柱状部分，电荷存储层和多个第一导电层的半导体层。 第二区域包括：与多个第一导电层形成在同一层中的多个第二导电层。 多个第一导电层在第一区域的附近的端部处构成阶梯部。 阶梯部形成为阶梯状，使得多个第一导电层的端部的位置彼此不同。 多个第二导电层形成为使得围绕第一区域的第二区域的端部附近的端部的位置基本上与基板垂直的方向排列。