Redundancy circuit of a semiconductor memory device
    41.
    发明授权
    Redundancy circuit of a semiconductor memory device 失效
    半导体存储器件的冗余电路

    公开(公告)号:US5576999A

    公开(公告)日:1996-11-19

    申请号:US491348

    申请日:1995-06-30

    IPC分类号: G11C29/00 G11C29/48 G11C7/00

    CPC分类号: G11C29/785 G11C29/48

    摘要: A redundancy circuit of the semiconductor memory device having a normal memory cell array for storing data, a redundant memory cell for repairing the fail cells in the normal memory, cell array, a normal decoder for receiving addresses and designating the normal memory cell, a redundancy decoder for selecting the redundant memory cell. The circuit includes a control part which is controlled by a control clock and has fuses for programming fail addresses of the addresses, to be applied, a transmission part which is controlled by an output signal of the control part and has a first path for outputting addresses in-phase with the addresses and a second path for outputting addresses out of phase with the addresses, thereby selecting the first path before repair to select both the normal memory cell and redundant memory cell by the normal and redundancy decoders, and cutting off the fuses corresponding to the fail addresses and selecting the second path during the repair to select the redundant memory cell by the redundancy decoder, thus enabling burn-in of both the normal memory cell and redundant memory cell during the burn-in test.

    摘要翻译: 具有用于存储数据的正常存储单元阵列的半导体存储器件的冗余电路,用于修复正常存储器中的故障单元的冗余存储单元,单元阵列,用于接收地址和指定正常存储单元的正常解码器,冗余 用于选择冗余存储器单元的解码器。 电路包括由控制时钟控制的控制部分,并且具有用于编程要应用的地址的失败地址的熔丝,由控制部分的输出信号控制的发送部分,并且具有用于输出地址的第一路径 与地址同相,以及用于输出地址与地址异相的第二路径,从而在修复之前选择第一路径以通过正常和冗余解码器选择正常存储器单元和冗余存储器单元,并且切断熔丝 对应于故障地址并且在修复期间选择第二路径以通过冗余解码器选择冗余存储器单元,从而在老化测试期间能够老化正常存储器单元和冗余存储器单元。

    MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    42.
    发明申请
    MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
    磁记忆体装置及其制造方法

    公开(公告)号:US20110053293A1

    公开(公告)日:2011-03-03

    申请号:US12915335

    申请日:2010-10-29

    IPC分类号: H01L21/62

    摘要: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

    摘要翻译: 磁存储器件包括公共线; 第一写入二极管,读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构,分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体, 写入线,读出线和第二写入线,分别连接到第一写入导体,磁隧道注入结构和第二写入导体。

    Memory devices and memory systems having the same
    43.
    发明申请
    Memory devices and memory systems having the same 有权
    具有相同的存储器件和存储器系统

    公开(公告)号:US20080080240A1

    公开(公告)日:2008-04-03

    申请号:US11902424

    申请日:2007-09-21

    IPC分类号: G11C16/00

    摘要: A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.

    摘要翻译: 公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。 非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列,用于交换数据的DRAM接口,与外部设备的命令和地址,用于响应于所述存储器单元选择所述存储器单元中的一个的控制器 对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器,对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元,并且每个动态存储单元具有一个具有浮体的晶体管。

    Data read circuit for use in a semiconductor memory and a memory thereof
    44.
    发明授权
    Data read circuit for use in a semiconductor memory and a memory thereof 有权
    用于半导体存储器的数据读取电路及其存储器

    公开(公告)号:US06982913B2

    公开(公告)日:2006-01-03

    申请号:US10943300

    申请日:2004-09-17

    IPC分类号: G11C7/00

    摘要: A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

    摘要翻译: 提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。 该电路包括:选择器,用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元,用于响应于钳位控制信号,将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元,用于响应于在预充电模式中的第一状态的控制信号而将感测节点预充电到具有电源电平的电压,并且响应于位线在位线处减小的电流量补偿 在数据感测模式中的第二状态的控制信号; 以及感测放大器单元,用于将感测节点的电平与参考电平进行比较,并且用于感测存储在所选择的单位单元中的数据。

    Semiconductor memory device and test method therof
    45.
    发明授权
    Semiconductor memory device and test method therof 有权
    半导体存储器件和测试方法

    公开(公告)号:US06781899B2

    公开(公告)日:2004-08-24

    申请号:US10202272

    申请日:2002-07-24

    IPC分类号: G11C2900

    摘要: A semiconductor memory device employs a power supply system in which a first power supply voltage supplied to a cell area is separated from a second power supply voltage supplied to a peripheral circuit area. Particularly, during a wafer burn-in test operation mode, the first power supply voltage supplied to the cell area is higher than the second power supply voltage supplied to the peripheral circuit area. If a wafer burn-in test operation is performed under the second power supply system, a DC current path formed by a latch-up phenomenon of a memory cell can be shut off.

    摘要翻译: 半导体存储器件采用电源系统,其中提供给单元区域的第一电源电压与提供给外围电路区域的第二电源电压分离。 特别地,在晶片老化测试操作模式期间,提供给单元区域的第一电源电压高于提供给外围电路区域的第二电源电压。 如果在第二电源系统下执行晶片老化测试操作,则可以切断由存储器单元的闩锁现象形成的直流电流路径。

    Static random access memory device with burn-in test circuit
    46.
    发明授权
    Static random access memory device with burn-in test circuit 失效
    具有老化测试电路的静态随机存取存储器

    公开(公告)号:US5956279A

    公开(公告)日:1999-09-21

    申请号:US19519

    申请日:1998-02-05

    IPC分类号: G11C11/413 G11C29/34 G11C7/00

    CPC分类号: G11C29/34

    摘要: A static random access memory (SRAM) device comprises an array of memory cells, a plurality of bit line precharge circuit for selectively delivering current to bit lines in response to a pair of control signals, during normal and burn-in test modes, and a burn-in current source circuit for selectively delivering current to the memory cells selected by the word lines along with the precharge circuit, in response to the control signals, during the burn-in test mode. In burn-in write operation, memory cells can be supplied with enough cell current without large increasing of chip size and power consumption in normal operation mode.

    摘要翻译: 静态随机存取存储器(SRAM)装置包括存储器单元阵列,多个位线预充电电路,用于在正常和老化测试模式期间响应于一对控制信号选择性地将电流输送到位线;以及 老化电流源电路,用于在老化测试模式期间响应于控制信号选择性地将电流与预充电电路一起输送到由字线选择的存储器单元。 在老化写入操作中,在正常操作模式下,存储单元可以提供足够的单元电流,而不会大大增加芯片尺寸和功耗。

    Burn-in circuit and method therefor of semiconductor memory device
    47.
    发明授权
    Burn-in circuit and method therefor of semiconductor memory device 失效
    老化电路及其半导体存储器件的方法

    公开(公告)号:US5471429A

    公开(公告)日:1995-11-28

    申请号:US348180

    申请日:1994-11-28

    CPC分类号: G11C29/34 G01R31/2856

    摘要: The present invention pertains to semiconductor memory devices and more particularly to a burn-in circuit of such devices and burn-in method which improve reliability of a static random access memory RAM. The semiconductor memory device according to the present invention, which includes a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, and a column decoder for selecting the column of the memory cell array, comprises an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, and a burn-in control circuit for inputting the output signal of the read/write control circuit, supplying a burn-in signal responsive to the data input through the input/output line control circuit to the row decoder and column decoder, and enabling a burn-in test of the same chip after a package process.

    摘要翻译: 本发明涉及半导体存储器件,更具体地说,涉及提高静态随机存取存储器RAM的可靠性的这种器件的老化电路和老化方法。 根据本发明的半导体存储器件,其包括存储单元阵列,其中多个存储器单元被存储在行和列的方向上,行解码器用于选择存储单元阵列的行,以及列解码器 用于选择存储单元阵列的列,包括形成在设置在同一芯片上的数据输入/输出引脚和存储单元阵列的列之间的输入/输出线控制电路,用于发送通过数据输入/ 输出引脚,用于将控制存储单元阵列中的数据的输入/输出的信号提供给输入/输出线控制电路的读/写控制电路,以及用于输入读/写控制电路的输出信号的老化控制电路, 写入控制电路,响应于通过输入/输出线路控制电路输入的数据向行解码器和列解码器提供老化信号,以及在一个包之后启用相同芯片的老化测试 年龄过程。

    Magnetic memory device and method of fabricating the same
    48.
    发明授权
    Magnetic memory device and method of fabricating the same 失效
    磁记忆装置及其制造方法

    公开(公告)号:US08043869B2

    公开(公告)日:2011-10-25

    申请号:US12915335

    申请日:2010-10-29

    IPC分类号: H01L29/82

    摘要: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

    摘要翻译: 磁存储器件包括公共线; 第一写入二极管,读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构,分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体, 写入线,读出线和第二写入线,分别连接到第一写入导体,磁隧道注入结构和第二写入导体。

    Data read circuit for use in a semiconductor memory and a method therefor
    50.
    发明申请
    Data read circuit for use in a semiconductor memory and a method therefor 有权
    用于半导体存储器的数据读取电路及其方法

    公开(公告)号:US20060034112A1

    公开(公告)日:2006-02-16

    申请号:US11249858

    申请日:2005-10-13

    IPC分类号: G11C11/00

    摘要: A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

    摘要翻译: 提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。 该电路包括:选择器,用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元,用于响应于钳位控制信号,将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元,用于响应于在预充电模式中的第一状态的控制信号,将感测节点预充电到具有电源电平的电压,并且响应于位线在位线处减少的电流量补偿 在数据感测模式中的第二状态的控制信号; 以及感测放大器单元,用于将感测节点的电平与参考电平进行比较,并且用于感测存储在所选择的单位单元中的数据。