公开(公告)号：US20080073694A1

公开(公告)日：2008-03-27

申请号：US11526149

申请日：2006-09-22

申请人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

发明人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

公开(公告)号：US07323388B2

公开(公告)日：2008-01-29

申请号：US11072695

申请日：2005-03-04

申请人： Joachim Deppe ,  Christoph Ludwig ,  Christoph Kleint ,  Josef Willer

发明人： Joachim Deppe ,  Christoph Ludwig ,  Christoph Kleint ,  Josef Willer

IPC分类号： H01L29/417

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.

摘要翻译： 在硅体（1）中制造沟槽（2）。 沟槽的壁（4）设置有氮注入（6）。 源极/漏极区域（5）和施加在顶侧的字线之间的氧化物层比在沟槽壁上制作为栅极电介质的ONO存储层的低氧化物层增长更大的厚度。 代替氮注入到沟槽壁中，可以在源极/漏极区的顶侧上制造金属硅化物层，以加速其中的氧化物生长。

公开(公告)号：US20070254428A1

公开(公告)日：2007-11-01

申请号：US11411994

申请日：2006-04-26

申请人： Josef Willer ,  Klaus-Dieter Ufert

发明人： Josef Willer ,  Klaus-Dieter Ufert

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L45/14 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/32 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1683

摘要： Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.

摘要翻译： 字线堆叠在衬底表面上彼此间隔一定距离平行排列。 位线横向于彼此间隔一定距离的字线堆栈布置。 源极/漏极区域形成为字线堆叠附近的掺杂区域。 电阻层设置在多个源极/漏极区域和位线之间，并且由具有通过施加电压切换的电阻的材料形成。 源极线平行于字线堆栈布置，使得它们连接更多个源极/漏极区域。

公开(公告)号：US20070178684A1

公开(公告)日：2007-08-02

申请号：US11344961

申请日：2006-01-31

申请人： Torsten Mueller ,  Josef Willer ,  Stephanie Iacono

发明人： Torsten Mueller ,  Josef Willer ,  Stephanie Iacono

IPC分类号： H01L21/44

CPC分类号： H01L27/0203 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/222

摘要： A periodic pattern of conductor tracks with broader interspaces is produced by the application of a totally periodic pattern and subsequent removal of individual conductor tracks. An alternative method comprises the formation of a completely periodic hardmask, from which individual parts are removed. The modified hardmask is then used to etch a periodic pattern of conductor tracks with intermediate broader spaces.

摘要翻译： 具有较宽空间的导体轨迹的周期性图案通过施加全周期图案并随后移除各个导体轨迹来产生。 一种替代方法包括形成完全周期性的硬掩模，从其中去除各个部件。 然后使用改进的硬掩模来蚀刻具有中间较宽空间的导体轨迹的周期性图案。

公开(公告)号：US20070082446A1

公开(公告)日：2007-04-12

申请号：US11246908

申请日：2005-10-07

申请人： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

发明人： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/115 ,  H01L21/76897 ,  H01L27/11568

摘要： A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

摘要翻译： 提供了用于制造堆叠的非易失性存储单元的方法。 提供具有形成埋入位线的多个扩散区域的半导体晶片。 电荷捕获层和导电层沉积在半导体晶片的表面上。 在导电层的顶部使用掩模层，形成绝缘层的接触孔。 蚀刻停止层沉积在半导体晶片的表面上。 在蚀刻停止层上方，沉积介电层并图案化以形成接触孔。 随后，接触孔通过蚀刻停止层和绝缘层扩大到埋入位线。

公开(公告)号：US07159786B2

公开(公告)日：2007-01-09

申请号：US10925882

申请日：2004-08-23

申请人： Jurgen Fischer ,  Herbert Palm ,  Frank Puschner ,  Josef Willer

发明人： Jurgen Fischer ,  Herbert Palm ,  Frank Puschner ,  Josef Willer

IPC分类号： G06K19/06

CPC分类号： G06K19/07747 ,  G06K19/07743 ,  H01L2224/48091 ,  H01L2924/00014

摘要： Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body, external contact elements arranged on the carrier and electrically connected to the chip via conductor runs, and a cover covering the recess in operative connection with the carrier such that the carrier is held along the bottom in the recess, wherein the external contact elements and the chip are arranged on a same side of the carrier.

摘要翻译： 数据载体卡具有扁平形式的卡体，并且具有凹槽，载体，布置在载体上的芯片并插入卡体的凹部中，外部接触元件布置在载体上并电连接到芯片通孔导体 并且覆盖与载体可操作地连接的凹部的盖，使得载体沿着凹部中的底部保持，其中外部接触元件和芯片布置在载体的同一侧上。

公开(公告)号：US07094648B2

公开(公告)日：2006-08-22

申请号：US11023041

申请日：2004-12-27

申请人： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig ,  Josef Willer

发明人： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig ,  Josef Willer

IPC分类号： H01L21/8236

CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

摘要： In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

摘要翻译： 在该方法中，蚀刻沟槽，并且在其间，位线（8）分别布置在掺杂的源极/漏极区域（3,4）上。 存储层（5,6,7）被施加，栅电极（2）布置在沟槽壁处。 在向栅极电极（2）引入向多个沟槽中引入的多晶硅之后，以平坦化的方式将顶面进行研磨，直到到达覆盖层（16）的顶侧，然后将多晶硅层 （18），其被设置用于字线，并且被图案化以形成字线。

公开(公告)号：US07087500B2

公开(公告)日：2006-08-08

申请号：US10894348

申请日：2004-07-19

申请人： Frank Lau ,  Josef Willer

发明人： Frank Lau ,  Josef Willer

IPC分类号： H01L21/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

摘要翻译： 存储单元包括在半导体本体的顶侧的源极/漏极区之间的沟道区，并且相对于纵向方向横向地设置有形成在半导体材料中的凸起。 这导致径向电场的强度的均匀分布，并且避免了在通道区​​域的横向边缘处的场强尖峰。 存储层序列位于通道区域和栅电极之间，作为字线的一部分。

公开(公告)号：US07049651B2

公开(公告)日：2006-05-23

申请号：US10715142

申请日：2003-11-17

申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.

摘要翻译： 电荷捕获层包括在源极和漏极结上方的两个条带。 选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。 通过将热孔单独注入热孔进行两位存储来执行编程。

公开(公告)号：US07041545B2

公开(公告)日：2006-05-09

申请号：US10795611

申请日：2004-03-08

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573

摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.