公开(公告)号：US06541816B2

公开(公告)日：2003-04-01

申请号：US09893026

申请日：2001-06-27

申请人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi S. Sunkavalli ,  Janet S. Wang ,  Narbeh Derhacobian

发明人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi S. Sunkavalli ,  Janet S. Wang ,  Narbeh Derhacobian

IPC分类号： H01L29792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954 ,  Y10S438/981

摘要： One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

公开(公告)号：US06529410B1

公开(公告)日：2003-03-04

申请号：US09665916

申请日：2000-09-20

申请人： Michael Han ,  Narbeh Derhacobian

发明人： Michael Han ,  Narbeh Derhacobian

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  H01L27/115

摘要： An efficient NAND array structure includes memory cells coupled in series between a bit-line and a select source transistor, without a select drain transistor. The memory cells each include a floating gate transistor, having a control gate connected to a word-line, which selects the memory cell during its programming. In one embodiment, the NAND array structure includes a buried layer at a junction between the substrate and a well in which the memory cells are formed. Programming is achieved using hot electron injection. In one embodiment, multiple memory cells are programmed simultaneously.

摘要翻译： 有效的NAND阵列结构包括串联耦合在位线和选择源晶体管之间的存储单元，而没有选择漏极晶体管。 每个存储单元都包括一个具有连接到字线的控制栅极的浮栅晶体管，其在编程期间选择该存储单元。 在一个实施例中，NAND阵列结构包括在衬底与其中形成存储器单元的阱之间的接合处的掩埋层。 使用热电子注入实现编程。 在一个实施例中，多个存储器单元被同时编程。

公开(公告)号：US06514830B1

公开(公告)日：2003-02-04

申请号：US10044510

申请日：2002-01-11

申请人： Hao Fang ,  Narbeh Derhacobian

发明人： Hao Fang ,  Narbeh Derhacobian

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11534

摘要： A method of manufacturing a high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect while avoiding an excessive number of costly masking steps. A high gated diode breakdown voltage is provided in the manufacturing process by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 一种制造高栅极二极管击穿电压，低泄漏和低体效应的高压晶体管的方法，同时避免过多数量的昂贵的掩蔽步骤。 在制造过程中通过掩蔽来自常规场注入的高压结和从常规阈值调整植入物屏蔽源极/漏极区域来提供高栅极二极管击穿电压。 在场注入阻挡掩模中形成有角度的开口，使得场离子注入距离结点不同的距离，从而实现低泄漏和高门控二极管击穿电压。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US06468865B1

公开(公告)日：2002-10-22

申请号：US09723653

申请日：2000-11-28

申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

公开(公告)号：US06351017B1

公开(公告)日：2002-02-26

申请号：US09533057

申请日：2000-03-22

申请人： Hao Fang ,  Narbeh Derhacobian

发明人： Hao Fang ,  Narbeh Derhacobian

IPC分类号： H01L31119

CPC分类号： H01L27/11526 ,  H01L27/11534

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 形成具有高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结以及从常规阈值调整植入物屏蔽源/漏区来提供高门控二极管击穿电压。 在场注入阻挡掩模中形成有角度的开口，使得场离子注入距离结点不同的距离，从而实现低泄漏和高门控二极管击穿电压。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US06228782B1

公开(公告)日：2001-05-08

申请号：US09309994

申请日：1999-05-11

申请人： Hao Fang ,  Massaki Higashitani ,  Narbeh Derhacobian

发明人： Hao Fang ,  Massaki Higashitani ,  Narbeh Derhacobian

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76216 ,  H01L27/115

摘要： Selective high-energy impurity implantation enables optimization of both core and peripheral field isolation without substantially degrading functionality, self-boosting efficiency or otherwise increasing program disturb, thereby improving device performance and reliability. Embodiments include high-energy impurity implantation, after forming core and peripheral field oxide regions in a semiconductor substrate, into the peripheral field oxide region and selected portions of the core field oxide regions corresponding to select transistor areas, while blocking the implant from the core memory cell channel regions. A channel stop implant is performed through the core field oxide regions after etching a first polysilicon layer. The high-energy impurity implant optimizes peripheral field isolation, without degrading self-boosting efficiency, because it is blocked from entering the memory cell channel region. The high-energy implant also enhances isolation in the select transistor areas, thereby preventing an increase in device malfunctions, while the channel stop implant optimizes core field isolation.

摘要翻译： 选择性高能杂质注入使得能够优化核和外围场隔离，而不会显着降低功能性，自增强效率或以其他方式增加程序干扰，从而提高器件性能和可靠性。 实施例包括在半导体衬底中形成核心和外围场氧化物区域之后的高能杂质注入到对应于选择晶体管区域的外围场氧化物区域和核心场氧化物区域的选定部分，同时将核心存储器 细胞通道区。 在蚀刻第一多晶硅层之后，通过核心场氧化物区域进行沟道停止注入。 高能杂质注入优化外围场隔离，而不会降低自增强效率，因为它被阻止进入存储单元通道区。 高能量注入还增强了选择晶体管区域的隔离度，从而防止了器件故障的增加，而通道停止植入则优化了磁芯隔离。

公开(公告)号：US5991202A

公开(公告)日：1999-11-23

申请号：US161423

申请日：1998-09-24

申请人： Narbeh Derhacobian ,  Hao Fang

发明人： Narbeh Derhacobian ,  Hao Fang

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C11/34

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/10

摘要： A NAND flash memory system is programmed with minimal program disturb and pass disturb during self-boosting without resorting to impurity implantation for bit line isolation, to p-well biasing or to bit line biasing techniques. A program voltage is applied to a selected word line in the form of a plurality of short pulses while synchronously applying a pulsed pass voltage to the unselected word lines until the selected cell is programmed. The duration of the pulses and the time between pulses are chosen to minimize the program disturb of unselected cells, especially unselected cells on the selected word line, without causing pass disturb of any cell in the array.

摘要翻译： NAND闪存系统被编程为在自增强期间具有最少的编程干扰和通过干扰，而不需要利用用于位线隔离的杂质注入，p阱偏置或位线偏置技术。 将编程电压以多个短脉冲的形式施加到所选择的字线，同时将脉冲通过电压同时施加到未选择的字线，直到所选择的单元被编程。 选择脉冲的持续时间和脉冲之间的时间以最小化未选择的单元，特别是所选字线上的未选择的单元的编程干扰，而不会引起阵列中的任何单元的通过干扰。

公开(公告)号：US08320148B1

公开(公告)日：2012-11-27

申请号：US12802506

申请日：2010-06-07

申请人： Narbeh Derhacobian

发明人： Narbeh Derhacobian

IPC分类号： G11C15/00

CPC分类号： G11C15/046 ,  G11C13/0011

摘要： Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.

摘要翻译： 本文公开了使用PMC的CAM单元的方法和电路。 在一个实施例中，BCAM单元可以包括：（i）耦合到第一存取晶体管和位节点的第一PMC，其中第一存取晶体管耦合到真位线; （ii）耦合到第二存取晶体管和所述位节点的第二PMC单元，其中所述第二存取晶体管耦合到补码位线，并且所述第一和第二存取晶体管由字线控制; （iii）耦合到所述位节点的编程使能晶体管，并且被配置为在使能时将编程控制电压耦合到所述位节点; 以及（iv）配置指示晶体管，被配置为响应于相对于所述位节点的真和补码位线的状态来放电匹配线。

公开(公告)号：US20090134910A1

公开(公告)日：2009-05-28

申请号：US12350219

申请日：2009-01-07

申请人： Colin Neal Murphy ,  Narbeh Derhacobian ,  Louis Charles Kordus, II ,  Antonietta Oliva ,  Vei-Han Chan ,  Thomas E. Stewart, JR.

发明人： Colin Neal Murphy ,  Narbeh Derhacobian ,  Louis Charles Kordus, II ,  Antonietta Oliva ,  Vei-Han Chan ,  Thomas E. Stewart, JR.

IPC分类号： H03K19/177 ,  G11C11/00

CPC分类号： G11C13/0011 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/025 ,  G11C23/00 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778

摘要： Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

摘要翻译： 可重构的电子结构和电路使用可编程的非易失性存储元件。 可编程的非易失性存储器元件可以执行存储和/或开关的功能，以产生诸如交叉开关，多路复用器，查找表（LUT）和在可编程逻辑结构（例如，（FPGA））中使用的其它逻辑电路的组件， ）。 可编程的非易失性存储元件包括基于相变存储器，可编程金属化，碳纳米机电（CNT-NEM）或金属纳米机电器件技术的一个或多个结构。

公开(公告)号：US20080206922A1

公开(公告)日：2008-08-28

申请号：US12116911

申请日：2008-05-07

申请人： Antonietta Oliva ,  Louis Charles Kordus ,  Narbeh Derhacobian ,  Vei-Han Chan ,  Thomas E. Stewart

发明人： Antonietta Oliva ,  Louis Charles Kordus ,  Narbeh Derhacobian ,  Vei-Han Chan ,  Thomas E. Stewart

IPC分类号： H01L45/00

CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/126

摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。