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公开(公告)号：US20060018149A1
公开(公告)日：2006-01-26
申请号：US10895218
申请日：2004-07-20
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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公开(公告)号：US08395928B2
公开(公告)日：2013-03-12
申请号：US13206460
申请日：2011-08-09
申请人： Julie Casperson Brewer , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Darrell Rinerson , Lawrence Schloss
发明人： Julie Casperson Brewer , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Darrell Rinerson , Lawrence Schloss
IPC分类号： G11C11/36
CPC分类号： G11C7/02 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/71 , G11C2213/76 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/147
摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.
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公开(公告)号：US20090303773A1
公开(公告)日：2009-12-10
申请号：US12456677
申请日：2009-06-18
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
摘要翻译： 公开了使用混合价态导电氧化物的记忆体。 存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。
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公开(公告)号：US07158397B2
公开(公告)日：2007-01-02
申请号：US11024279
申请日：2005-04-14
IPC分类号： G11C5/06
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line drivers is on a first side of the cross point array and the other portion is on the opposite side. However, using this technique requires that the width of the drivers is no larger than the width of the memory cells that are being driven. This can be accomplished by stacking transistors such that line drivers fit within a specified line pitch, but are as long as is necessary to include all the necessary circuitry.
摘要翻译： 适合指定线路间距的线路驱动器。 将线驱动器完全放置在交叉点阵列下方的一种方法需要将线驱动器向上分开，使得线驱动器的一部分位于交叉点阵列的第一侧，而另一部分在相对侧。 然而，使用这种技术要求驱动器的宽度不大于被驱动的存储单元的宽度。 这可以通过堆叠晶体管来实现，使得线路驱动器适合指定的线间距，但是必须包括所有必要的电路。
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公开(公告)号：US20060245241A1
公开(公告)日：2006-11-02
申请号：US11478520
申请日：2006-06-29
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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46.发明授权Non-volatile memory with a single transistor and resistive memory element 失效具有单个晶体管和电阻式存储器元件的非易失性存储器公开(公告)号：US07126841B2
公开(公告)日：2006-10-24
申请号：US11061101
申请日：2005-02-18
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/2409 , H01L27/2436 , H01L27/2445 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.
摘要翻译： 每个存储单元具有单个半导体器件的非易失性存储器单元。 本发明通常允许在支撑半导体器件的半导体衬底上形成多个存储单元。 通常在非常高的温度下，在衬底上方形成在施加电压脉冲时改变其电阻状态在低电阻状态和高电阻状态之间的多电阻状态材料层。 虽然在衬底和多电阻状态材料之间制造的层使用可承受高温处理的材料，但是在多电阻状态材料之上制造的层不需要经受高温处理。
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公开(公告)号：US07095643B2
公开(公告)日：2006-08-22
申请号：US11151880
申请日：2005-06-13
IPC分类号： G11C5/06
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C2213/31
摘要： A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.
摘要翻译： 具有多个内存层的可重写内存。 只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。 通过多层共享逻辑可以重新使用驱动程序集。
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公开(公告)号：US07054183B2
公开(公告)日：2006-05-30
申请号：US11218655
申请日：2005-09-02
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2013/0066 , G11C2213/31
摘要： A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing resistance while programming the memory cell. The programming circuit can be used to only program the memory cell for as long as programming is actually needed. Additionally, the programming circuit can be used to only program the memory cell when it has a value that needs to be changed.
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公开(公告)号：US07020006B2
公开(公告)日：2006-03-28
申请号：US10922202
申请日：2004-08-18
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： Circuitry that discharges conductive array lines is provided. Generally, the conductive array lines are simultaneously selected and apply an appropriate programming pulse. Accordingly, the conductive array lines need to be discharged in connection with a write operation. The discharge can occur either prior to or following a write operation.
摘要翻译： 提供放电导电阵列线路的电路。 通常，同时选择导电阵列线并施加适当的编程脉冲。 因此，导电阵列线需要与写入操作相关地放电。 放电可以在写入操作之前或之后发生。
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50.发明申请公开(公告)号：US20060007769A1
公开(公告)日：2006-01-12
申请号：US11218655
申请日：2005-09-02
IPC分类号： G11C7/02
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2013/0066 , G11C2213/31
摘要： A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing resistance while programming the memory cell. The programming circuit can be used to only program the memory cell for as long as programming is actually needed. Additionally, the programming circuit can be used to only program the memory cell when it has a value that needs to be changed.
摘要翻译： 提供了编程电路。 由于导电存储单元被编程，其电阻变化。 所提供的编程电路在编程存储器单元时监视变化的电阻。 只要编程实际需要，编程电路就可以用于只对存储单元进行编程。 此外，编程电路可以用于仅当存储单元具有需要改变的值时对其进行编程。
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