Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions
    45.
    发明申请
    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions 审中-公开
    金属氧化物半导体场效应晶体管(MOSFET)包括嵌入式通道区域

    公开(公告)号:US20110079831A1

    公开(公告)日:2011-04-07

    申请号:US12966362

    申请日:2010-12-13

    IPC分类号: H01L29/772

    摘要: Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

    摘要翻译: 金属氧化物半导体(MOS)晶体管的单位电池在集成电路基板上具有集成电路基板和MOS晶体管。 MOS晶体管包括源极区,漏极区和栅极。 栅极在源极区域和漏极区域之间。 在源区和漏区之间提供沟道区。 沟道区具有比源区和漏区的底表面低的凹陷区域。 还提供了制造晶体管的相关方法。

    SEMICONDUCTOR DEVICES
    47.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开
    半导体器件

    公开(公告)号:US20100117152A1

    公开(公告)日:2010-05-13

    申请号:US12687286

    申请日:2010-01-14

    申请人: Chang-Woo Oh

    发明人: Chang-Woo Oh

    IPC分类号: H01L29/786 H01L21/336

    摘要: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.

    摘要翻译: 提供一种半导体器件。 半导体器件包括半导体衬底,半导体衬底上的第一隔离电介质图案和第一隔离电介质图案上的有源图案。 在半导体衬底和第一隔离电介质图案之间插入半导体图案,并且在半导体衬底和半导体图案之间插入第二隔离电介质图案。 半导体衬底和半导体图案通过连接图案电连接。

    Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same
    48.
    发明申请
    Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same 有权
    具有增加的源极/漏极接触面积的垂直沟道鳍效应晶体管及其制造方法

    公开(公告)号:US20100044784A1

    公开(公告)日:2010-02-25

    申请号:US12613025

    申请日:2009-11-05

    IPC分类号: H01L29/78

    摘要: A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

    摘要翻译: 翅片场效应晶体管(FinFET)器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。

    SEMICONDUCTOR DEVICE HAVING FLOATING BODY ELEMENT AND BULK BODY ELEMENT AND METHOD OF MANUFACTURING THE SAME
    50.
    发明申请
    SEMICONDUCTOR DEVICE HAVING FLOATING BODY ELEMENT AND BULK BODY ELEMENT AND METHOD OF MANUFACTURING THE SAME 有权
    具有浮动体元素和体积体元素的半导体器件及其制造方法

    公开(公告)号:US20090001503A1

    公开(公告)日:2009-01-01

    申请号:US12146016

    申请日:2008-06-25

    IPC分类号: H01L21/86 H01L27/12

    摘要: A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided.

    摘要翻译: 提供了具有浮体元件和本体元件的半导体器件及其制造方法。 半导体器件包括具有块体元件区域和浮体元件区域的衬底。 隔离区域限定衬底的本体元件区域的有源区域,并且限定顺序地堆叠在衬底的浮体元件区域的第一元件区域上的第一掩埋图案和第一有源图案。 设置介于第一掩埋图案和基板之间以及第一掩埋图案和第一有源图案之间的第一掩埋介质层。