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    SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME 审中-公开
    具有源极和漏极绝缘区域的单晶体管存储器件及其制造方法

    公开(公告)号：US20110042746A1

    公开(公告)日：2011-02-24

    申请号：US12940304

    申请日：2010-11-05

    申请人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

    发明人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

    IPC分类号： H01L29/772

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/7834 ,  H01L29/7841

    摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

    摘要翻译： 单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。 源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。 浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

    Fin field effect transistors including oxidation barrier layers
    4.
    发明授权
    Fin field effect transistors including oxidation barrier layers 有权
    鳍场效应晶体管包括氧化阻挡层

    公开(公告)号：US07745871B2

    公开(公告)日：2010-06-29

    申请号：US11871453

    申请日：2007-10-12

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7854 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78645

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

    SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICES USING VOID SPACES
    5.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICES USING VOID SPACES 审中-公开
    半导体绝缘体（SOI）器件使用空隙

    公开(公告)号：US20100127328A1

    公开(公告)日：2010-05-27

    申请号：US12696125

    申请日：2010-01-29

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L27/12

    CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

    摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

    摘要翻译： 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

    Methods of fabricating surrounded-channel transistors with directionally etched gate or insulator formation regions
    6.
    发明授权
    Methods of fabricating surrounded-channel transistors with directionally etched gate or insulator formation regions 有权
    用定向蚀刻的栅极或绝缘体形成区域制造环绕晶体管的方法

    公开(公告)号：US07396726B2

    公开(公告)日：2008-07-08

    申请号：US11095969

    申请日：2005-03-31

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Sung-Young Lee

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Sung-Young Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78645 ,  Y10S438/924

    摘要： An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed. The hollow may be filled with a gate electrode that completely surrounds the exposed portion of the second semiconductor material region, or the gate electrode may partially surround the exposed portion of the second semiconductor material region and an insulation region may be formed in the hollow.

    摘要翻译： 在衬底上形成细长的堆叠半导体结构。 层叠的半导体结构包括设置在第一半导体材料区域上的第二半导体材料区域。 第一半导体材料区域被选择性地掺杂以产生间隔杂质掺杂的第一半导体材料区域和其间的较低掺杂浓度的第一半导体材料区域。 蚀刻使杂质掺杂的第一半导体材料区域之间的第二半导体材料区域的一部分暴露。 蚀刻去除下掺杂剂浓度的第一半导体材料区域的至少一部分，以在衬底与掺杂杂质的第一半导体材料区域之间的第二半导体材料区域的部分之间形成中空。 形成了在杂质掺杂的第一半导体材料区域之间围绕第二半导体材料区域的暴露部分的绝缘层。 中空部可以填充有完全围绕第二半导体材料区域的暴露部分的栅电极，或者栅电极可以部分地围绕第二半导体材料区域的暴露部分，并且可以在中空部中形成绝缘区域。

    SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES AND SEMICONDUCTOR DEVICES USING VOID SPACES
    7.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES AND SEMICONDUCTOR DEVICES USING VOID SPACES 审中-公开
    半导体绝缘体（SOI）衬底和使用空隙的半导体器件

    公开(公告)号：US20070257312A1

    公开(公告)日：2007-11-08

    申请号：US11774240

    申请日：2007-07-06

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

    摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

    摘要翻译： 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

    SEMICONDUCTOR DEVICE HAVING TWO DIFFERENT OPERATION MODES EMPLOYING AN ASYMMETRICAL BURIED INSULATING LAYER AND METHOD FOR FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE HAVING TWO DIFFERENT OPERATION MODES EMPLOYING AN ASYMMETRICAL BURIED INSULATING LAYER AND METHOD FOR FABRICATING THE SAME 审中-公开
    具有使用不对称的绝缘绝缘层的两种不同操作模式的半导体器件及其制造方法

    公开(公告)号：US20070184611A1

    公开(公告)日：2007-08-09

    申请号：US11696132

    申请日：2007-04-03

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10802 ,  H01L27/0214 ,  H01L27/10873 ,  H01L29/7841 ,  H01L29/78612

    摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

    摘要翻译： 根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。 掩埋绝缘层插入在下半导体衬底和上硅图案之间。 穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。 当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时， 漏极电压施加到该区域。

    Stacked integrated circuit device including multiple substrates and method of manufacturing the same
    10.
    发明申请
    Stacked integrated circuit device including multiple substrates and method of manufacturing the same 审中-公开
    包括多个基板的堆叠集成电路器件及其制造方法

    公开(公告)号：US20050110159A1

    公开(公告)日：2005-05-26

    申请号：US10977702

    申请日：2004-10-28

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L23/12 ,  H01L21/762 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06 ,  H01L29/04

    CPC分类号： H01L21/76251 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a stacked integrated circuit device including multiple substrates and a method of manufacturing the same. A first integrated circuit substrate, a first integrated circuit formed on the first integrated circuit substrate, and a first passivation insulating layer are sequentially formed. Then, wafer bonding technique for forming an SOI substrate is used, thereby forming a second integrated circuit substrate on the first passivation insulating layer. While forming a second integrated circuit on the second integrated circuit substrate, at least one device-connecting interconnect electrically connects the first and second Integrated circuits and penetrates the second integrated circuit substrate and the first passivation layer. A second passivation insulating layer is formed on an upper surface of the second integrated circuit.

    摘要翻译： 提供了包括多个基板的堆叠集成电路器件及其制造方法。 依次形成第一集成电路基板，形成在第一集成电路基板上的第一集成电路和第一钝化绝缘层。 然后，使用用于形成SOI衬底的晶片接合技术，从而在第一钝化绝缘层上形成第二集成电路衬底。 当在第二集成电路衬底上形成第二集成电路时，至少一个器件连接互连电连接第一和第二集成电路并且穿透第二集成电路衬底和第一钝化层。 第二钝化绝缘层形成在第二集成电路的上表面上。