公开(公告)号：US06177349B1

公开(公告)日：2001-01-23

申请号：US09206169

申请日：1998-12-07

申请人： Diana M. Schonauer ,  Steven C. Avanzino ,  Kai Yang

发明人： Diana M. Schonauer ,  Steven C. Avanzino ,  Kai Yang

IPC分类号： H01L2144

CPC分类号： H01L21/7684 ,  H01L21/76819

摘要： The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP by immersion in and/or double sided brush scrubbing with a chemical agent. Embodiments include removing controlled portions up to 50 Å of silicon oxide by immersion in and/or double sided brush scrubbing with a solution containing ammonium fluoride, diammonium hydrogen citrate, triammonium citrate, a surfactant and dionized water.

摘要翻译： 从Cu或Cu合金线发射到边界开放介质场中的枝晶的形成和/或生长通过从介电场中化学去除表面的一部分和CMP之后的线之间的浸入和/ 或用化学试剂双面刷洗。 实施例包括通过用含有氟化铵，柠檬酸氢铵，柠檬酸三铵，表面活性剂和二价离子水的溶液浸渍和/或双面刷洗来去除高达50埃的氧化硅的受控部分。

公开(公告)号：US07776682B1

公开(公告)日：2010-08-17

申请号：US11110165

申请日：2005-04-20

申请人： Alexander Nickel ,  Suzette K. Pangrle ,  Steven C. Avanzino ,  Jeffrey Shields ,  Fei Wang ,  Minh Tran ,  Juri H. Krieger ,  Igor Sokolik

发明人： Alexander Nickel ,  Suzette K. Pangrle ,  Steven C. Avanzino ,  Jeffrey Shields ,  Fei Wang ,  Minh Tran ,  Juri H. Krieger ,  Igor Sokolik

IPC分类号： H01L21/8242

CPC分类号： H01L45/1233 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/141 ,  H01L45/142 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1616

摘要： Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.

摘要翻译： 公开了用于改善记忆单元中电性能的细胞间细胞重复性的方法和系统。 所述方法包括在无源层上形成具有有序孔隙率的非导电材料。 有序孔隙度可以促进导电通道的形成，电荷载体可以穿过导​​电通道迁移穿过另外的非导电层以便于改变存储器单元的状态。 可以可选地在非导电层上形成阻挡层，并且可以以基本上垂直于导电沟道的方式定向排序的孔隙，使得穿过非导电层迁移的电荷不能渗透到阻挡层。 该方法提供了具有成本效益和电可靠性的存储单元的微电子器件的制造。

公开(公告)号：US07465408B1

公开(公告)日：2008-12-16

申请号：US10726992

申请日：2003-12-03

申请人： Steven C. Avanzino

发明人： Steven C. Avanzino

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C23F3/00

CPC分类号： C23F1/18 ,  C23C22/52 ,  C23C22/83 ,  H01L21/02074 ,  H01L21/32134 ,  H01L21/67115 ,  H01L21/67248 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are methods and systems of etching copper containing materials so that they have smooth and/or planar surface. In this connection, the systems and methods employ two different solutions to accomplish the etching. The first solution oxidizes the surface of the copper containing material and forms a passivating film. The second solution removes the passivating film in a controlable manner.

摘要翻译： 公开了蚀刻含铜材料的方法和系统，使得它们具有平滑和/或平坦的表面。 在这方面，系统和方法采用两种不同的解决方案来完成蚀刻。 第一种溶液氧化含铜材料的表面并形成钝化膜。 第二种溶液以可控的方式去除钝化膜。

公开(公告)号：US06720264B2

公开(公告)日：2004-04-13

申请号：US09749191

申请日：2000-12-26

申请人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Johannes F. Groschopf ,  Gerd F. C. Marxsen ,  Steven C. Avanzino

发明人： Kashmir S. Sahota ,  Diana M. Schonauer ,  Johannes F. Groschopf ,  Gerd F. C. Marxsen ,  Steven C. Avanzino

IPC分类号： H01L21302

CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/3212

摘要： A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation. The organic additive-containing slurry cain be utilized throughout the entire polish time. Alternatively, a slurry not containing the organic additive can be utilized for a first portion of the polish, and a slurry containing the organic additive or a polishing solution containing the organic additive can be utilized for a second portion of the polish.

摘要翻译： 在铜金属化期间用于化学机械抛光（CMP）的Ta阻挡浆料包含抑制沉淀物形成和铜污染的有机添加剂。 有机添加剂选自一类化合物，其形成与二氧化硅或铜的表面的多个强吸附剂键，其在反应性物质上提供高度的表面覆盖度，从而占据潜在的反应位点，并且它们的大小适于空间阻碍 两个反应物分子之间的碰撞导致新的键形成。 在整个抛光时间内可以使用含有机添加剂的浆料。 或者，不含有机添加剂的浆料可用于抛光剂的第一部分，并且含有有机添加剂的浆料或含有有机添加剂的抛光溶液可用于第二部分抛光剂。

公开(公告)号：US06702648B1

公开(公告)日：2004-03-09

申请号：US10277559

申请日：2002-10-22

申请人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： B24B4900

CPC分类号： B24B37/013 ,  B24B49/12

摘要： One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.

摘要翻译： 本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。 该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统，使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器，其中每个传感器的至少一部分被集成到抛光系统中，以便向计量系统提供数据，并且其中传感器包括至少一个光学元件以在抛光期间检测分层。 该方法包括抛光最上面的薄膜层的至少一部分，并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。

公开(公告)号：US06684172B1

公开(公告)日：2004-01-27

申请号：US10034165

申请日：2001-12-27

申请人： Ramkumar Subramanian ,  Steven C. Avanzino ,  Christopher F. Lyons ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Cyrus E. Tabery

发明人： Ramkumar Subramanian ,  Steven C. Avanzino ,  Christopher F. Lyons ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Cyrus E. Tabery

IPC分类号： G01L2500

CPC分类号： C23C16/52 ,  C23C14/547 ,  C23C18/1675 ,  C25D21/12 ,  H01L21/76877

摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.

摘要翻译： 本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。 本发明还涉及其工具表征过程及其系统。

公开(公告)号：US06548336B2

公开(公告)日：2003-04-15

申请号：US10067765

申请日：2002-02-08

申请人： Steven C. Avanzino ,  Steven K. Park

发明人： Steven C. Avanzino ,  Steven K. Park

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L21/32055 ,  H01L21/3212 ,  H01L27/115

摘要： A new device and technique to realize an improved integrated circuit device incorporates an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

摘要翻译： 实现改进的集成电路器件的新器件和技术结合了改进的多晶硅上表面。 这种改进通过近似平坦化多晶硅层的上表面来实现。 首先，与常规器件中的层厚相比，多晶硅层优选形成为相对较厚的层。 然后，优选利用化学机械抛光技术去除多晶硅层的一部分。 因此，本实施例实现了多晶硅层的相对平坦化的上表面。 然后，例如，可以在相对平坦化的多晶硅层上形成常规的金属或硅化物层。 多晶硅层的近似平坦化的上表面允许形成硅化物层，其中常规字线空隙和接缝的量和/或严重性相对降低。

公开(公告)号：US06433379B1

公开(公告)日：2002-08-13

申请号：US09777571

申请日：2001-02-06

申请人： Sergey Lopatin ,  Steven C. Avanzino ,  Qi Xiang ,  Matthew Buynoski

发明人： Sergey Lopatin ,  Steven C. Avanzino ,  Qi Xiang ,  Matthew Buynoski

IPC分类号： H01L2972

CPC分类号： H01L28/40 ,  H01L21/2885 ,  H01L21/31687

摘要： The present invention relates to a method for forming in-laid copper metallization capacitors in a trench serpentine form. In one aspect of the present invention, the method includes providing a semiconductor substrate having at least one trench formed therein. A first metal layer is deposited conformally onto a trench and substrate surface. The first metal layer is then anodized to form a conformal bilayer comprising an anodic (metal) oxide layer formed over the first metal layer. A copper-conductive metal layer is then deposited conformally over the metal oxide layer to facilitate electroplating of the trench and substrate surface. The trench and substrate surface is then electroplated with copper whereby the at least one trench is filled with copper.

摘要翻译： 本发明涉及一种以沟槽蛇形形式形成埋入式铜金属化电容器的方法。 在本发明的一个方面，所述方法包括提供其中形成有至少一个沟槽的半导体衬底。 第一金属层保形地沉积在沟槽和衬底表面上。 然后阳极氧化第一金属层以形成包含在第一金属层上形成的阳极（金属）氧化物层的共形双层。 然后将铜导电金属层保形地沉积在金属氧化物层上以促进沟槽和衬底表面的电镀。 然后用铜电镀沟槽和衬底表面，由此至少一个沟槽填充有铜。

公开(公告)号：US06326305B1

公开(公告)日：2001-12-04

申请号：US09730696

申请日：2000-12-05

申请人： Steven C. Avanzino ,  Diana M. Shonauer

发明人： Steven C. Avanzino ,  Diana M. Shonauer

IPC分类号： H01L21302

CPC分类号： H01L21/02074 ,  C09G1/02 ,  H01L21/3212

摘要： An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. The conductor core and barrier layer are chemical-mechanical polished. The dielectric layer is then chemically-mechanically polished using a slurry containing ceria, a Ce(IV) oxide. Residual ceria on the conductor core and dielectric layer is then removed using a reducing agent to react the Ce(IV) oxide to the Ce(III) oxide for removal in an aqueous solution.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路制造方法。 在半导体衬底上形成器件电介质层。 器件电介质层上的沟道电介质层具有形成在其中的开口。 屏障层对通道开口进行排列。 导体芯填充阻挡层上的开口。 导体芯和阻挡层进行化学机械抛光。 然后使用含有二氧化铈，Ce（IV）氧化物的浆料对介电层进行化学机械抛光。 然后使用还原剂除去导体芯和电介质层上的残余二氧化铈，以使Ce（IV）氧化物与Ce（III）氧化物反应，以在水溶液中除去。

公开(公告)号：US06319833B1

公开(公告)日：2001-11-20

申请号：US09207318

申请日：1998-12-07

申请人： Diana M. Schonauer ,  Steven C. Avanzino ,  Kai Yang

发明人： Diana M. Schonauer ,  Steven C. Avanzino ,  Kai Yang

IPC分类号： H01L21302

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP by spraying the wafer with a chemical agent. Embodiments include removing up to 60Å of silicon oxide by spraying the wafer with an acidic solution, such as a solution comprising acetic acid and ammonium fluoride.

摘要翻译： 从Cu或Cu合金线发射到边界开放的介电场中的枝晶的形成和/或生长通过从介电场中化学去除表面的一部分以及CMP之后的线之间，通过将晶片与 化学剂。 实施例包括通过用酸性溶液（例如包含乙酸和氟化铵的溶液）喷洒晶片去除多达60埃的氧化硅。