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公开(公告)号：US06766468B2
公开(公告)日：2004-07-20
申请号：US09682023
申请日：2001-07-11
IPC分类号： H02H305
CPC分类号： G11C29/44 , G11C29/72 , G11C2029/1208
摘要： A method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.
摘要翻译： 内存BIST（内置自检）和内存修复方法，用于存储片上冗余计算，而不是将数据片外扫描以备以后使用。 该方法不再需要对测试仪进行片外存储器冗余数据的电平敏感扫描设计（LSSD）扫描，因此不需要再次接触芯片进行电熔丝熔断。
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公开(公告)号：US06249470B1
公开(公告)日：2001-06-19
申请号：US09454265
申请日：1999-12-03
IPC分类号： G11C702
CPC分类号： G11C11/419 , G11C7/065
摘要： According to the preferred embodiment, a device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment, the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.
摘要翻译： 根据优选实施例，提供了一种用于降低存储器件中的功耗的装置和方法。 优选实施例通过提供在提供高性能的同时降低功耗的读出放大器来降低功耗。 在优选实施例中，读出放大器包括可配置用于低功率静态随机存取存储器（SRAM）器件的双向读出放大器。 双向读出放大器允许将相同的感测放大器用于存储器单元上的读取和写入操作。 优选实施例的感测放大器有助于使用差分数据总线，进一步降低功耗，同时提供高性能。 因此，优选实施例的双向差分检测放大器降低了器件尺寸和复杂性，降低了功耗，同时提供了高性能的存储器访问。
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公开(公告)号：US08661399B1
公开(公告)日：2014-02-25
申请号：US13567127
申请日：2012-08-06
IPC分类号： G06F17/50
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译： 本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。 在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。
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44.发明授权公开(公告)号：US08595678B2
公开(公告)日：2013-11-26
申请号：US13365370
申请日：2012-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译： 公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。 检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接 块和其他逻辑块。
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公开(公告)号：US20130205268A1
公开(公告)日：2013-08-08
申请号：US13365370
申请日：2012-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译： 公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。 检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接 块和其他逻辑块。
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公开(公告)号：US20130042166A1
公开(公告)日：2013-02-14
申请号：US13204929
申请日：2011-08-08
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译： 选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。 可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。 每个状态机可以包括当遇到其类型的校正时可以被激活的指示器，例如粘性位。 指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。
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47.发明申请CIRCUIT AND METHOD FOR ASYNCHRONOUS PIPELINE PROCESSING WITH VARIABLE REQUEST SIGNAL DELAY 有权具有可变请求信号延迟的异步管道加工的电路和方法公开(公告)号：US20120062300A1
公开(公告)日：2012-03-15
申请号：US12882425
申请日：2010-09-15
IPC分类号： H03H11/26
CPC分类号： G06F5/10 , G06F2205/104
摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.
摘要翻译： 公开了异步管线电路的实施例。 在电路的每个阶段，可变延迟线被并入到请求信号路径中。 抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。 基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟 信号沿请求信号路径传输。 使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。 还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。
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公开(公告)号：US08024626B2
公开(公告)日：2011-09-20
申请号：US11552166
申请日：2006-10-24
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , H03K19/1735
摘要： A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.
摘要翻译： 一种用于修复半导体芯片中的有缺陷的存储器的方法和系统。 该芯片具有存储器位置，冗余存储器和用于有序保险丝的中心位置。 有序保险丝以压缩格式识别存储器位置的缺陷部分。 有缺陷的部分可由冗余存储器的部分替换。 有序保险丝具有相关联的熔丝位模式，其顺序地表示压缩格式的缺陷部分。 方法和系统确定存储器位置连接在一起的顺序; 根据存储器位置连接在一起的顺序，通过存储器位置设计锁存器的移位寄存器; 并且将每个锁存器与从其导出熔丝位模式的未压缩位模式的对应位相关联。 未压缩比特模式包括一个比特序列，表示未压缩格式的缺陷部分。
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公开(公告)号：US07710800B2
公开(公告)日：2010-05-04
申请号：US11954479
申请日：2007-12-12
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C5/14 , G11C29/83 , G11C2029/4402
摘要： An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions.
摘要翻译： 描述了管理电压岛中的冗余存储器的方法。 在一个实施例中，存在体现在用于半导体器件的设计过程中的机器可读介质中的设计结构。 在该实施例中，设计结构包括代表功率循环区域的一个或多个电压岛。 一个或多个非功率循环区域位于一个或多个电压岛周围。 一个或多个非功率循环区域中的每一个包括使用冗余的至少一个存储器和与使用冗余的每个存储器相关联的修复寄存器。 冗余初始化组件耦合到一个或多个电压岛和一个或多个非功率循环区域。
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公开(公告)号：US07702975B2
公开(公告)日：2010-04-20
申请号：US12099382
申请日：2008-04-08
CPC分类号： H03K19/018585 , H03K19/018557 , H03K19/018592
摘要： A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality.
摘要翻译： 用于集成电路结构的方法，集成电路结构和相关联的设计结构具有多个逻辑块，其中至少一个是冗余逻辑块。 此外，该结构包括逻辑内置自检装置（LBIST），其可操作地连接到确定每个逻辑块的功能的逻辑块。 存储器元件阵列包括在结构内并且可操作地连接到逻辑块。 存储器元件中的至少一个包括冗余存储元件。 该结构还包括可操作地连接到确定每个存储器元件的功能的存储器元件阵列的阵列内置自检器件（ABIST）。 一个特征是使用可操作地连接到寄存器，逻辑块和存储器元件的单个控制器。 单个控制器修复具有故障功能的逻辑块元素和具有故障功能的存储器元件。
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