公开(公告)号：US20110032757A1

公开(公告)日：2011-02-10

申请号：US12536127

申请日：2009-08-05

申请人： Deepanshu Dutta ,  Henry Chin

发明人： Deepanshu Dutta ,  Henry Chin

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

摘要翻译： 根据其WLn-1相邻存储元件的状态，通过在分离的组中对所选字线WLn上的存储元件进行编程来对非易失性存储系统中的程序干扰进行减少，并且对于每一个，向WLn-1施加最佳的通过电压 组。 最初，读取WLn-1上的存储元件的状态。 程序迭代包括多个程序脉冲。 当向WLn-1施加第一通过电压时，将第一编程脉冲施加到WLn，选择第一组WLn存储元件进行编程，并且禁止第二组WLn存储元件。 接下来，向WLn施加第二编程脉冲，同时将第二通过电压施加到WLn-1，选择第二组WLn存储元件进行编程，并且禁止第一组WLn存储元件。 组可以包括一个或多个数据状态。

公开(公告)号：US08638606B2

公开(公告)日：2014-01-28

申请号：US13234539

申请日：2011-09-16

申请人： Dengtao Zhao ,  Guirong Liang ,  Deepanshu Dutta

发明人： Dengtao Zhao ,  Guirong Liang ,  Deepanshu Dutta

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C2211/5644 ,  G11C2211/565

摘要： A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count.

摘要翻译： 公开了一种降低非易失性存储系统中的程序干扰的编程技术。 在编程期间可以将正电压施加到衬底（例如，p阱）。 偏置衬底可以提高未选择的NAND串的通道的升高，这可能减少程序干扰。 在编程操作期间可以对衬底进行充电，并在编程之后放电。 因此，对于诸如验证和读取的操作，衬底可以接地。 在一个实施例中，在施加编程脉冲之前对衬底进行充电，然后在程序验证操作之前被放电。 在一个实施例中，在未选择的字线斜坡上升到通过电压的同时对衬底进行充电。 衬底偏置可能取决于程序电压，温度和/或热计数。

公开(公告)号：US20130314995A1

公开(公告)日：2013-11-28

申请号：US13479649

申请日：2012-05-24

申请人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

发明人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C7/1006 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.

摘要翻译： 一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。 非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。 通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。 选择栅极晶体管的电压也可以电容耦合得更高。 衬底电压可以逐步增加和/或作为连续斜坡增加。 在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。 在另一种方法中，外部和内部虚拟存储元件都浮起来。 由于基板中的电荷捕获减少，存储元件的写擦除耐久性增加。

公开(公告)号：US08451667B2

公开(公告)日：2013-05-28

申请号：US13360103

申请日：2012-01-27

申请人： Jeffrey W Lutze ,  Deepanshu Dutta

发明人： Jeffrey W Lutze ,  Deepanshu Dutta

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.

摘要翻译： 非易失性存储系统通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的程序干扰，这增加了禁止信道的钳位升压电位以避免程序干扰。 交替的相邻位线对被分组成第一和第二组。 第一组对的非易失性存储元件经受编程脉冲并且在第一迭代次数中的每一个中验证操作，之后第二组对的非易失性存储元件经受编程脉冲并且验证操作 每次迭代次数为次。

公开(公告)号：US20130070530A1

公开(公告)日：2013-03-21

申请号：US13622045

申请日：2012-09-18

申请人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

发明人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/063 ,  G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

摘要翻译： 公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

公开(公告)号：US08320177B2

公开(公告)日：2012-11-27

申请号：US13370410

申请日：2012-02-10

申请人： Deepanshu Dutta ,  Henry Chin

发明人： Deepanshu Dutta ,  Henry Chin

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

公开(公告)号：US08223556B2

公开(公告)日：2012-07-17

申请号：US12625883

申请日：2009-11-25

申请人： Deepanshu Dutta ,  Gerrit Jan Hemink

发明人： Deepanshu Dutta ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method and non-volatile storage system are provided in which programming speed is increased by reducing the number of verify operations, while maintaining a narrow threshold voltage distribution. A programming scheme performs a verify operation at an offset level, before a verify level of a target data state is reached, such as to slow down programming. However, it is not necessary to perform verify operations at both the offset and target levels at all times. In a first programming phase, verify operations are performed for a given data state only at the target verify level. In a second programming phase, verify operations are performed for offset and target verify levels. In a third programming phase, verify operations are again performed only at the target verify level. Transitions between phases can be predetermined, based on programming pulse number, or adaptive.

摘要翻译： 提供了一种方法和非易失性存储系统，其中通过减少验证操作的数量来增加编程速度，同时保持窄的阈值电压分布。 在达到目标数据状态的验证级别之前，编程方案在偏移级别执行验证操作，例如减慢编程。 但是，始终不必在偏移量和目标电平两者上执行验证操作。 在第一个编程阶段，仅在目标验证级别对给定数据状态执行验证操作。 在第二个编程阶段，对偏移和目标验证电平执行验证操作。 在第三个编程阶段，仅在目标验证级别再次执行验证操作。 相位之间的转换可以根据编程脉冲数或自适应来预先确定。

公开(公告)号：US20120140568A1

公开(公告)日：2012-06-07

申请号：US13370410

申请日：2012-02-10

申请人： Deepanshu Dutta ,  Henry Chin

发明人： Deepanshu Dutta ,  Henry Chin

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

摘要翻译： 根据其WLn-1相邻存储元件的状态，通过在分离的组中对所选字线WLn上的存储元件进行编程来对非易失性存储系统中的程序干扰进行减少，并且对于每一个，向WLn-1施加最佳的通过电压 组。 最初，读取WLn-1上的存储元件的状态。 程序迭代包括多个程序脉冲。 当向WLn-1施加第一通过电压时，将第一编程脉冲施加到WLn，选择第一组WLn存储元件进行编程，并且禁止第二组WLn存储元件。 接下来，向WLn施加第二编程脉冲，同时将第二通过电压施加到WLn-1，选择第二组WLn存储元件进行编程，并且禁止第一组WLn存储元件。 组可以包括一个或多个数据状态。

公开(公告)号：US08130556B2

公开(公告)日：2012-03-06

申请号：US12398368

申请日：2009-03-05

申请人： Jeffrey W. Lutze ,  Deepanshu Dutta

发明人： Jeffrey W. Lutze ,  Deepanshu Dutta

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

摘要翻译： 编程技术通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的编程干扰，这增加了禁止信道的钳位升压电位以避免编程干扰。 一个方面将交替的相邻位线对组合成第一和第二组。 双编程脉冲被施加到选定的字线。 第一组位线在第一脉冲期间被编程，并且第二组位线在第二脉冲期间被编程。 然后对所有位线执行验证操作。 当特定位线被禁止时，其相邻位线中的至少一个也将被禁止，使得特定位线的通道将被充分提升。 另一个方面分别编写每第三个位线。 修改的布局允许使用奇偶校验感测电路来感测相邻的位线对。

公开(公告)号：US20120014184A1

公开(公告)日：2012-01-19

申请号：US12838902

申请日：2010-07-19

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454 ,  G11C16/3486 ,  G11C2216/14

摘要： Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state. The start and stop of the step up in the bit line voltage can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state-dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias.

摘要翻译： 使用编程技术使非易失性存储器件中的阈值电压分布变窄，并且/或编程时间减少，其中具有目标数据状态的存储元件的位线电压被升高，在升压锁定步骤中 在编程电压。 根据其目标数据状态，针对存储元件的不同子集，在编程遍历中的不同时刻对位线电压进行升压。 可以基于固定的编程脉冲数或基于编程进度的自适应来设置位线电压中的升压的开始和停止。 变化包括使用固定的位线步长，变化的位线步长，数据状态相关的位线步长，不增加一个或多个数据状态的位线的选项以及增加额外位线偏置的选项。