公开(公告)号：US20130070531A1

公开(公告)日：2013-03-21

申请号：US13234539

申请日：2011-09-16

申请人： Dengtao Zhao ,  Guirong Liang ,  Deepanshu Dutta

发明人： Dengtao Zhao ,  Guirong Liang ,  Deepanshu Dutta

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C2211/5644 ,  G11C2211/565

摘要： A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count.

摘要翻译： 公开了一种降低非易失性存储系统中的程序干扰的编程技术。 在编程期间可以将正电压施加到衬底（例如，p阱）。 偏置衬底可以提高未选择的NAND串的通道的升高，这可能减少程序干扰。 在编程操作期间可以对衬底进行充电，并在编程之后放电。 因此，对于诸如验证和读取的操作，衬底可以接地。 在一个实施例中，在施加编程脉冲之前对衬底进行充电，然后在程序验证操作之前被放电。 在一个实施例中，在未选择的字线斜坡上升到通过电压的同时对衬底进行充电。 衬底偏置可取决于程序电压，温度和/或热计数。

公开(公告)号：US08638606B2

公开(公告)日：2014-01-28

申请号：US13234539

申请日：2011-09-16

申请人： Dengtao Zhao ,  Guirong Liang ,  Deepanshu Dutta

发明人： Dengtao Zhao ,  Guirong Liang ,  Deepanshu Dutta

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C2211/5644 ,  G11C2211/565

摘要： A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count.

摘要翻译： 公开了一种降低非易失性存储系统中的程序干扰的编程技术。 在编程期间可以将正电压施加到衬底（例如，p阱）。 偏置衬底可以提高未选择的NAND串的通道的升高，这可能减少程序干扰。 在编程操作期间可以对衬底进行充电，并在编程之后放电。 因此，对于诸如验证和读取的操作，衬底可以接地。 在一个实施例中，在施加编程脉冲之前对衬底进行充电，然后在程序验证操作之前被放电。 在一个实施例中，在未选择的字线斜坡上升到通过电压的同时对衬底进行充电。 衬底偏置可能取决于程序电压，温度和/或热计数。

公开(公告)号：US08472255B2

公开(公告)日：2013-06-25

申请号：US13605714

申请日：2012-09-06

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US20100258851A1

公开(公告)日：2010-10-14

申请号：US12757812

申请日：2010-04-09

申请人： Jianlin Liu ,  Dengtao Zhao ,  Yan Zhu ,  Ruigang Li ,  Bei Li

发明人： Jianlin Liu ,  Dengtao Zhao ,  Yan Zhu ,  Ruigang Li ,  Bei Li

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825

摘要： Nanocrystal memories and methods of making the same are disclosed. In one embodiment, a memory device comprises a substrate, a tunneling oxide, a silicide nanocrystal floating gate, and a control oxide. The tunneling oxide is positioned upon a first surface of the substrate, the silicide nanocrystal floating gate is positioned upon the tunneling oxide, and the control oxide positioned upon the nanocrystal floating gate.

摘要翻译： 公开了纳米晶体存储器及其制造方法。 在一个实施例中，存储器件包括衬底，隧道氧化物，硅化物纳米晶体浮动栅极和控制氧化物。 隧道氧化物位于衬底的第一表面上，硅化物纳米晶体浮栅位于隧道氧化物上，并且控制氧化物位于纳米晶体浮栅上。

公开(公告)号：US07463528B2

公开(公告)日：2008-12-09

申请号：US11958534

申请日：2007-12-18

申请人： Nima Mokhlesi ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Dengtao Zhao

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C7/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.

摘要翻译： 使用非选择字线的温度补偿读取电压和/或用于NAND串的漏极或源极选择栅极的选择栅极对非易失性存储元件执行读取和验证操作。 在一种方法中，当读取或验证电压被施加到所选择的字线时，温度补偿的读取电压被施加到未选择的字线并选择栅极。 直接与所选字线相邻的字线可以接收不被温度补偿的电压，或者被降低程度的温度补偿。 施加到所选字线的读取或验证电压也可以进行温度补偿。 温度补偿也可以说明字线位置。

公开(公告)号：US20080273388A1

公开(公告)日：2008-11-06

申请号：US11688874

申请日：2007-03-21

申请人： Henry Chin ,  Nima Mokhlesi ,  Dengtao Zhao

发明人： Henry Chin ,  Nima Mokhlesi ,  Dengtao Zhao

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454

摘要： In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistances associated with the data memory cells can be changed to account for different programmed data patterns.

摘要翻译： 在一些非易失性存储系统中，在块的底部，块的顶部和/或其他位置处制造具有伪字线的数据存储单元块。 通过选择性地编程虚拟字线上的存储器单元，可以改变与数据存储单元相关联的电阻以考虑不同的编程数据模式。

公开(公告)号：US20080244338A1

公开(公告)日：2008-10-02

申请号：US11694947

申请日：2007-03-31

申请人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

IPC分类号： G11C29/00

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果解码失败，则从存储器读取软数据位。 在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。 在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。 当在比较级的第二子集读取时，可以基于第一子集数据执行解码。

公开(公告)号：US20070291566A1

公开(公告)日：2007-12-20

申请号：US11424800

申请日：2006-06-16

申请人： Nima Mokhlesi ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Dengtao Zhao

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C7/04 ,  G11C16/06

CPC分类号： G11C7/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.

摘要翻译： 使用非选择字线的温度补偿读取电压和/或用于NAND串的漏极或源极选择栅极的选择栅极对非易失性存储元件执行读取和验证操作。 在一种方法中，当读取或验证电压被施加到所选择的字线时，温度补偿的读取电压被施加到未选择的字线并选择栅极。 直接与所选字线相邻的字线可以接收不被温度补偿的电压，或者被降低程度的温度补偿。 施加到所选字线的读取或验证电压也可以进行温度补偿。 温度补偿也可以说明字线位置。

公开(公告)号：US08468424B2

公开(公告)日：2013-06-18

申请号：US13024676

申请日：2011-02-10

申请人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F12/00 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/028 ,  H03M13/11 ,  H03M13/37

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge.

摘要翻译： 使用迭代概率解码和多次读取操作来解码存储在非易失性存储器中的数据，以实现更高的可靠性。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的读取数据。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果没有发生收敛，例如在设定的时间周期内，再次感测到非易失性存储元件的状态，则调整解码器中的可靠性度量的当前值，并且解码再次尝试收敛。

公开(公告)号：US20110252283A1

公开(公告)日：2011-10-13

申请号：US13164401

申请日：2011-06-20

申请人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

IPC分类号： G06F11/25

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果解码失败，则从存储器读取软数据位。 在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。 在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。 当在比较级的第二子集读取时，可以基于第一子集数据执行解码。