公开(公告)号：US5939335A

公开(公告)日：1999-08-17

申请号：US3107

申请日：1998-01-06

申请人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

发明人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/336

CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

公开(公告)号：US5492718A

公开(公告)日：1996-02-20

申请号：US349230

申请日：1994-12-05

申请人： James A. O'Neill ,  Michael L. Passow ,  Tina J. Cotler ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  Jyothi Singh

发明人： James A. O'Neill ,  Michael L. Passow ,  Tina J. Cotler ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  Jyothi Singh

IPC分类号： G01N21/33 ,  C23C16/44 ,  C23C16/455 ,  C23C16/52 ,  C23F4/00 ,  G01N21/35 ,  H01L21/205 ,  H01L21/302 ,  H01L21/31 ,  H01L31/00 ,  B05D3/06 ,  C23C8/00

CPC分类号： G01N21/3504 ,  C23C16/52

摘要： An apparatus for processing a layer on a workpiece includes a source of reactant fluid, a reaction chamber having a support for the workpiece and a fluid delivery apparatus for feeding an input fluid into the reaction chamber with the input fluid being utilized to process the material. An infrared sensor is adapted to cooperate with the fluid delivery apparatus for sensing the concentration of a component of the input fluid. The infrared sensor includes an infrared light source positioned to direct a beam of infrared light at an infrared light detector through the input fluid. The infrared light detector produces an electrical output signal indicative of the amount of light received by the detector and therefore not absorbed by the input fluid.

摘要翻译： 用于处理工件上的层的设备包括反应物流体源，具有用于工件的支撑的反应室和用于将输入流体输送到反应室中的流体输送装置，其中输入流体用于处理材料。 红外传感器适于与流体输送装置配合，用于感测输入流体的组分的浓度。 红外传感器包括红外光源，其被定位成通过输入流体引导红外光检测器处的​​红外光束。 红外光检测器产生指示由检测器接收的光量的电输出信号，因此不被输入流体吸收。

公开(公告)号：US5328868A

公开(公告)日：1994-07-12

申请号：US989742

申请日：1992-12-10

申请人： Richard A. Conti ,  Kenneth DeVries ,  James F. White

发明人： Richard A. Conti ,  Kenneth DeVries ,  James F. White

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76877 ,  Y10S148/05 ,  Y10S148/073

摘要： A metal connection for an integrated circuit device is effectively "cast" in place at any level of an integrated circuit. The "mold" for the connection is formed by depositing and patterning a sacrificial material, such as aluminum oxide or other metal oxides, and covering the sacrificial material with a protective material such as silicon dioxide or other insulators. After forming bore holes to the deposit of sacrificial material through the protective layer, the sacrificial material is removed by isotropic etching to form a cavity beneath and at least partially overlaid by the protective layer. Alternatively, a defect may be produced below the protective layer and filled with metal either with or without enlargement by further removal of material. This cavity is then filled with metal by deposition of the metal by, for instance, evaporation, sputtering and chemical vapor deposition or combinations thereof. Connections formed by this technique can be produced at any level of the integrated circuit and do not interfere with surface wiring. A plurality of such connections may be simultaneously formed at the same or different levels of the integrated circuit and the method may be repeated to form multi-level wiring patterns.

摘要翻译： 用于集成电路器件的金属连接在集成电路的任何级别上有效地“铸造”到位。 用于连接的“模具”通过沉积和图案化牺牲材料（例如氧化铝或其它金属氧化物）并用诸如二氧化硅或其它绝缘体的保护材料覆盖牺牲材料而形成。 在通过保护层沉积牺牲材料的孔之后，通过各向同性蚀刻去除牺牲材料，以在保护层下方并且至少部分地覆盖保护层。 或者，可以在保护层下面产生缺陷，并通过进一步去除材料来填充有或没有放大的金属。 然后通过例如蒸发，溅射和化学气相沉积或其组合通过沉积金属来填充该空腔。 通过该技术形成的连接可以在集成电路的任何级别产生，并且不会干扰表面布线。 可以在集成电路的相同或不同级别同时形成多个这样的连接，并且可以重复该方法以形成多层布线图案。

公开(公告)号：US07998871B2

公开(公告)日：2011-08-16

申请号：US12145915

申请日：2008-06-25

申请人： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

发明人： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

IPC分类号： H01L21/302

CPC分类号： H01L21/266 ,  H01L21/26513 ,  Y10T428/24992

摘要： Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

摘要翻译： 形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。 在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。 注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。 方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

公开(公告)号：US07804136B2

公开(公告)日：2010-09-28

申请号：US11875217

申请日：2007-10-19

申请人： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

发明人： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

IPC分类号： H01L23/62

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US07326651B2

公开(公告)日：2008-02-05

申请号：US10905068

申请日：2004-12-14

申请人： Heidi Baks ,  Richard A. Bruff ,  Richard A. Conti ,  Allan Upham

发明人： Heidi Baks ,  Richard A. Bruff ,  Richard A. Conti ,  Allan Upham

IPC分类号： H01L21/302

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76804

摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

摘要翻译： 本发明涉及集成电路器件中的双镶嵌互连结构的制造。 具体地，公开了一种利用平面化材料和压缩扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。 阻挡材料优选具有大于300MPa的压缩应力。 在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。 然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。 在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。 然后可以将所得的双镶嵌结构金属化。 通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

公开(公告)号：US20070275563A1

公开(公告)日：2007-11-29

申请号：US11420321

申请日：2006-05-25

申请人： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

发明人： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/266 ,  H01L21/26513 ,  Y10T428/24992

摘要： Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

摘要翻译： 形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。 在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。 注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。 方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

公开(公告)号：US07138717B2

公开(公告)日：2006-11-21

申请号：US10904827

申请日：2004-12-01

申请人： Yun-Yu Wang ,  Richard A. Conti ,  Chung-Ping Eng ,  Matthew C. Nicholls

发明人： Yun-Yu Wang ,  Richard A. Conti ,  Chung-Ping Eng ,  Matthew C. Nicholls

IPC分类号： H01L29/40

CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

摘要翻译： 一种覆盖氮化物叠层，可以防止蚀刻渗透到HDP氮化物，同时保持在Cu顶部的HDP氮化物的电迁移效果。 在一个实施例中，堆叠包括第一层HDP氮化物和设置在第一层上的Si-C-H化合物的第二层。 Si-C-H化合物例如是BLoK或N-BLoK（Si-C-H-N），并且选自在通孔RIE期间具有高选择性的一组材料，使得来自下一个布线层的RIE化学不会穿透。 碳氮是关键要素。 在另一个实施例中，堆叠包括第一层HDP氮化物，随后是第二层UVN（等离子体氮化物），以及包含设置在第二层上的HDP氮化物的第三层。

公开(公告)号：US06946345B2

公开(公告)日：2005-09-20

申请号：US10688612

申请日：2003-10-17

申请人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

发明人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

IPC分类号： H01L21/8242 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L27/10867 ,  H01L27/10864 ,  H01L29/945

摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

摘要翻译： 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

公开(公告)号：US06177344B1

公开(公告)日：2001-01-23

申请号：US09199911

申请日：1998-11-25

申请人： Li-Qun Xia ,  Richard A. Conti ,  Maria Galiano ,  Ellie Yieh

发明人： Li-Qun Xia ,  Richard A. Conti ,  Maria Galiano ,  Ellie Yieh

IPC分类号： H01L214763

CPC分类号： H01L21/31051 ,  H01L21/3105 ,  H01L21/31625

摘要： A multistep method for planarizing a silicon oxide insulating layer such as a deposited borophosphosilicate glass (BPSG) layer. The method includes several different planarization stages. During an initial, pre-planarization stage, a substrate having a BPSG layer deposited over it is loaded into a substrate processing chamber. Then, during a first planarization stage after the pre-planarization stage, oxygen and hydrogen are flowed into the substrate processing chamber to form a steam ambient in said chamber and the substrate is heated in the steam ambient from a first temperature to a second temperature. The first temperature is below a reflow temperature of the BPSG layer and the second temperature is sufficient to reflow the layer. After the substrate is heated to the second temperature during a second planarization stage, the temperature of the substrate and the conditions within the substrate processing chamber are maintained at conditions sufficient to reflow the BPSG layer in the steam ambient. In a more preferred embodiment, the multistep planarization method also includes a third planarization stage, after the second stage. In the third planarization stage, the flow of hydrogen is stopped while the flow of oxygen is maintained, thereby forming an oxygen ambient in the substrate processing chamber. The substrate temperature is maintained in the oxygen ambient at a temperature above the reflow temperature of the BPSG layer. It is believed that this additional step minimizes the amount of moisture incorporated into the reflowed BPSG layer.

摘要翻译： 一种用于平坦化氧化硅绝缘层例如沉积的硼磷硅酸盐玻璃（BPSG）层的多步法。 该方法包括几个不同的平坦化阶段。 在初始预平坦化阶段期间，在其上沉积有BPSG层的衬底被加载到衬底处理室中。 然后，在预平坦化阶段之后的第一平坦化阶段期间，氧气和氢气流入基板处理室以在所述室中形成蒸汽环境，并且基板在蒸汽环境中从第一温度加热到第二温度。 第一温度低于BPSG层的回流温度，第二温度足以使该层回流。 在第二平坦化阶段将衬底加热到​​第二温度之后，衬底的温度和衬底处理室内的条件保持在足以在蒸汽环境中回流BPSG层的条件。 在更优选的实施例中，多级平面化方法还包括在第二级之后的第三平坦化级。 在第三平坦化阶段，在保持氧气流的同时停止氢的流动，从而在衬底处理室中形成氧环境。 在超过BPSG层的回流温度的温度下，将基板温度保持在氧环境中。 据信这个附加步骤使并入回流的BPSG层中的水分量最小化。