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1.发明授权Method of forming nitride films with high compressive stress for improved PFET device performance 失效形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法公开(公告)号：US07491660B2
公开(公告)日：2009-02-17
申请号：US11873721
申请日：2007-10-17
申请人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/31 , H01L21/469 , C23C16/00 , C23C14/10 , C23C14/00
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。
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2.发明授权Method of forming nitride films with high compressive stress for improved PFET device performance 失效形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法公开(公告)号：US07462527B2
公开(公告)日：2008-12-09
申请号：US11160705
申请日：2005-07-06
申请人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。
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3.发明授权Method of forming nitride films with high compressive stress for improved PFET device performance 有权形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法公开(公告)号：US07804136B2
公开(公告)日：2010-09-28
申请号：US11875217
申请日：2007-10-19
申请人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
IPC分类号： H01L23/62
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。
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4.发明授权Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species 有权通过使用有机分子物种的气体簇的GCIB表面处理来修复工艺引起的介电损伤的方法公开(公告)号：US07838428B2
公开(公告)日：2010-11-23
申请号：US11609040
申请日：2006-12-11
IPC分类号： H01L21/311
CPC分类号： H01L21/3105 , H01L21/31155 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76831
摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method of repairing process induced dielectric damage from forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes treating an exposed area of the ILD material to create a carbon-rich area, and metallizing the carbon-rich area. One embodiment includes providing treatment to an exposed sidewall area of the ILD material to create a carbon-rich area by irradiating the exposed area using a gas cluster ion beam (GCIB) generated through a gas including a straight chain or branched, aliphatic or aromatic hydrocarbon, and metallizing the carbon-rich area.
摘要翻译： 当互连结构构建在多孔超低k（ULK）材料上时，沟槽和/或通孔的底部和/或侧壁通常被以下金属化或清洁工艺损坏，这可能适合于较高的介电材料。 本发明的实施例可以提供一种通过在层间电介质（ILD）材料上形成互连结构来修复工艺引起的介电损伤的方法。 该方法包括处理ILD材料的暴露区域以产生富含碳的区域，以及使富含碳的区域金属化。 一个实施例包括通过使用通过包括直链或支链，脂族或芳族烃的气体产生的气体簇离子束（GCIB）照射暴露区域来向ILD材料的暴露的侧壁区域提供处理以产生富碳区域 ，并且富含碳的区域金属化。
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5.发明申请METHOD OF REPAIRING PROCESS INDUCED DIELECTRIC DAMAGE BY THE USE OF GCIB SURFACE TREATMENT USING GAS CLUSTERS OF ORGANIC MOLECULAR SPECIES 有权通过使用有机分子物种的气体组合使用GCIB表面处理来修复过程诱导的电介质损伤的方法公开(公告)号：US20070224824A1
公开(公告)日：2007-09-27
申请号：US11609040
申请日：2006-12-11
IPC分类号： H01L21/311
CPC分类号： H01L21/3105 , H01L21/31155 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76831
摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method of repairing process induced dielectric damage from forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes treating an exposed area of the ILD material to create a carbon-rich area, and metallizing the carbon-rich area. One embodiment includes providing treatment to an exposed sidewall area of the ILD material to create a carbon-rich area by irradiating the exposed area using a gas cluster ion beam (GCIB) generated through a gas including a straight chain or branched, aliphatic or aromatic hydrocarbon, and metallizing the carbon-rich area.
摘要翻译： 当互连结构构建在多孔超低k（ULK）材料上时，沟槽和/或通孔的底部和/或侧壁通常被以下金属化或清洁工艺损坏，这可能适合于较高的介电材料。 本发明的实施例可以提供一种通过在层间电介质（ILD）材料上形成互连结构来修复工艺引起的介电损伤的方法。 该方法包括处理ILD材料的暴露区域以产生富含碳的区域，以及使富含碳的区域金属化。 一个实施例包括通过使用通过包括直链或支链，脂族或芳族烃的气体产生的气体簇离子束（GCIB）照射暴露区域来向ILD材料的暴露的侧壁区域提供处理以产生富碳区域 ，并且富含碳的区域金属化。
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公开(公告)号：US07407875B2
公开(公告)日：2008-08-05
申请号：US11470349
申请日：2006-09-06
CPC分类号： H01L21/76846 , H01L21/76856
摘要： Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.
摘要翻译： 本发明的实施例提供一种在半导体器件和后端串联之间的电介质材料层中制造接触结构的方法。 该方法包括在所述介电材料层中形成至少一个接触开口; 通过化学气相沉积工艺形成第一TiN膜，所述第一TiN膜衬在所述接触开口上; 以及通过物理气相沉积工艺形成第二TiN膜，所述第二TiN膜衬在所述第一TiN膜上。 还提供了根据本发明的实施例制造的接触结构。
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7.发明申请METHOD FOR IMPROVED FORMATION OF NICKEL SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES 失效用于改善在半导体器件中形成镍硅化物接触的方法公开(公告)号：US20080138985A1
公开(公告)日：2008-06-12
申请号：US11567517
申请日：2006-12-06
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.
摘要翻译： 形成用于半导体器件的硅化物触点的方法包括在约250至约400℃的初始脱气温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移至沉积室， 将晶片从脱气室转移到沉积室之后，在晶片上方的镍含量层，以及对半导体晶片进行退火，以在晶片上形成硅材料的部分上形成硅化物区域，其中镍材料形成在硅上。
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8.发明授权Method for improved formation of cobalt silicide contacts in semiconductor devices 失效用于改善半导体器件中的硅化钴接触的形成的方法公开(公告)号：US07485572B2
公开(公告)日：2009-02-03
申请号：US11534714
申请日：2006-09-25
IPC分类号： H01L29/45
CPC分类号： H01L21/28518
摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in time when the semiconductor wafer has cooled to temperature range of about 275-300° C., depositing a cap layer over the cobalt layer, and annealing the semiconductor wafer so as to create silicide contacts at portions on the wafer where cobalt is formed over silicon.
摘要翻译： 一种形成用于半导体器件的硅化物接触的方法包括在约400℃的温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移到沉积室，在晶片上沉积钴层 在半导体晶片已经冷却到约275-300℃的温度范围的时间点，在钴层上沉积覆盖层，并对半导体晶片进行退火，以在晶片上的部分形成硅化物接触，其中钴 在硅上形成。
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9.发明申请METHOD FOR IMPROVED FORMATION OF COBALT SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES 失效用于改善在半导体器件中形成钴硅氧烷接触的方法公开(公告)号：US20080124925A1
公开(公告)日：2008-05-29
申请号：US11534714
申请日：2006-09-25
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in time when the semiconductor wafer has cooled to temperature range of about 275-300° C., depositing a cap layer over the cobalt layer, and annealing the semiconductor wafer so as to create silicide contacts at portions on the wafer where cobalt is formed over silicon.
摘要翻译： 一种形成用于半导体器件的硅化物接触的方法包括在约400℃的温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移到沉积室，在晶片上沉积钴层 在半导体晶片已经冷却到约275-300℃的温度范围的时间点，在钴层上沉积覆盖层，并对半导体晶片进行退火，以在晶片上的部分形成硅化物接触，其中钴 在硅上形成。
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公开(公告)号：US20080054326A1
公开(公告)日：2008-03-06
申请号：US11470349
申请日：2006-09-06
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/76846 , H01L21/76856
摘要： Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.
摘要翻译： 本发明的实施例提供一种在半导体器件和后端串联之间的电介质材料层中制造接触结构的方法。 该方法包括在所述介电材料层中形成至少一个接触开口; 通过化学气相沉积工艺形成第一TiN膜，所述第一TiN膜衬在所述接触开口上; 以及通过物理气相沉积工艺形成第二TiN膜，所述第二TiN膜衬在所述第一TiN膜上。 还提供了根据本发明的实施例制造的接触结构。
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