公开(公告)号：US07016255B2

公开(公告)日：2006-03-21

申请号：US10876231

申请日：2004-06-23

申请人： Ihl-Ho Lee ,  Kyung-Whan Kim ,  Jae-Jin Lee

发明人： Ihl-Ho Lee ,  Kyung-Whan Kim ,  Jae-Jin Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1075 ,  G11C8/16 ,  G11C11/4097 ,  G11C29/846 ,  G11C2207/002

摘要： A multi-port memory device can avoid failure of the first high data during initial operation so that reliability and operation characteristic of the memory device can be improved. The multi-port memory device comprises a global data bus having a multiplicity of bus lines, a plurality of banks having a current sensing type transceiving structure for exchanging data with the global data bus, one or more ports having a current sensing type transceiving structure for exchanging data with the global data bus, a plurality of switches, each arranged between the corresponding bank and the bus lines of the global data bus for selectively connecting one of a redundant column and normal columns of the corresponding bank to the global data bus, and a controlling unit for restricting the turn-on period of the switches to the substantial operation period of the corresponding bank.

摘要翻译： 多端口存储器件可以避免初始操作期间第一高数据的故障，从而可以提高存储器件的可靠性和操作特性。 多端口存储器件包括具有多条总线线路的全局数据总线，多个存储体具有用于与全局数据总线交换数据的电流检测型收发结构，具有电流检测型收发结构的一个或多个端口 与全局数据总线交换数据，多个开关，每个交换机布置在全局数据总线的对应组和总线之间，用于选择性地将对应组的冗余列和正常列之一连接到全局数据总线;以及 控制单元，用于将开关的导通周期限制到相应银行的实质操作周期。

公开(公告)号：US20050225379A1

公开(公告)日：2005-10-13

申请号：US10982165

申请日：2004-11-05

申请人： Jae-Hyuk Im ,  Jae-Jin Lee

发明人： Jae-Hyuk Im ,  Jae-Jin Lee

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C11/4063 ,  G11C11/4074 ,  G11C11/413 ,  H03L5/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4068

摘要： Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column path & control logic and data path & control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.

摘要翻译： 本文公开了一种半导体存储器件的内部电压产生电路，其能够根据存储器件的不同操作模式向存储器件中的列路径和控制逻辑以及数据路径和控制逻辑提供不同电平的电压。 列路径和控制逻辑以及数据路径和控制逻辑在其参与存储器件的当前操作模式时被应用于正常工作电压，而当它们不涉及时具有较低的电压。 因此，本发明具有有效地管理半导体存储器件的内部电压并且减少存储器件的电流泄漏的效果，并且反过来又导致其不必要的功耗。

公开(公告)号：US5914641A

公开(公告)日：1999-06-22

申请号：US907480

申请日：1997-08-11

申请人： Kwang-Jun Yun ,  Chang-Seok Lee ,  Seong-Jae Maeng ,  Jae-Jin Lee

发明人： Kwang-Jun Yun ,  Chang-Seok Lee ,  Seong-Jae Maeng ,  Jae-Jin Lee

IPC分类号： H03F3/20 ,  H03F1/02 ,  H03F1/30 ,  H03F3/193 ,  H03G3/30 ,  H03F3/191

CPC分类号： H03F1/0272 ,  H03F1/301 ,  H03F3/1935 ,  H03G3/3042 ,  H03F2200/18 ,  H03F2200/318

摘要： A gate voltage control circuit of a power amplifier for reducing the power dissipation by improving the efficiency at an average output power and for enhancing the linearity of the power amplifier at a maximum output power, the gate voltage control circuit comprising an input terminal for receiving an output power signal from a power amplifier; an output power detecting circuit for detecting the output power signal and for converting the detected output power signal to a DC voltage signal; a voltage dividing circuit comprising at least two resistors for dividing a voltage difference between the DC voltage signal and a negative voltage in a ratio of resistances of the resistors; and an output terminal for supplying the divided voltage as a gate voltage control signal.

摘要翻译： 一种功率放大器的栅极电压控制电路，用于通过提高平均输出功率的效率并以最大的输出功率来提高功率放大器的线性来降低功耗，所述栅极电压控制电路包括：输入端子，用于接收 来自功率放大器的输出功率信号; 输出功率检测电路，用于检测输出功率信号并将检测到的输出功率信号转换成DC电压信号; 分压电路，包括至少两个电阻器，用于以所述电阻器的电阻的比率分压所述直流电压信号和负电压之间的电压差; 以及用于将分压电压提供为栅极电压控制信号的输出端子。

公开(公告)号：US08164710B2

公开(公告)日：2012-04-24

申请号：US12355993

申请日：2009-01-19

申请人： Dae-Won Kim ,  Kyung-Nam Kim ,  Jae-Jin Lee

发明人： Dae-Won Kim ,  Kyung-Nam Kim ,  Jae-Jin Lee

IPC分类号： G02F1/1335

CPC分类号： G02F1/133615 ,  G02B6/0073 ,  G02F1/133617

摘要： A backlight assembly includes a light guide plate and a light-emitting module. The light guide plate guides light. The light-emitting module is disposed to face an incidence surface of the light guide plate. The light-emitting module includes a printed circuit board (PCB) vertically disposed to face the incidence surface and a plurality of LEDs mounted on the PCB to emit light toward the incidence surface. Each of the LEDs includes a blue chip emitting blue light, a red fluorescent substance and a green fluorescent substance for converting the blue light into white light. Therefore, a thickness of the backlight assembly is reduced and an LED-mounting stability of the LED is improved.

摘要翻译： 背光组件包括导光板和发光模块。 导光板引导灯。 发光模块设置成面对导光板的入射表面。 发光模块包括垂直设置为面对入射表面的印刷电路板（PCB）和安装在PCB上的多个LED，以朝向入射表面发光。 每个LED包括发出蓝光的蓝色芯片，红色荧光物质和用于将蓝色光转换成白色光的绿色荧光物质。 因此，背光组件的厚度减小，LED的LED安装稳定性提高。

公开(公告)号：US07580313B2

公开(公告)日：2009-08-25

申请号：US11589038

申请日：2006-10-30

申请人： Dong-Keun Kim ,  Jae-Jin Lee

发明人： Dong-Keun Kim ,  Jae-Jin Lee

IPC分类号： G11C8/00

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/18 ,  G11C2207/105

摘要： A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.

摘要翻译： 一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。 半导体存储器件包括：具有第一和第二单元区域的单元区域; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

公开(公告)号：US07579821B2

公开(公告)日：2009-08-25

申请号：US11529255

申请日：2006-09-29

申请人： Kang-Seol Lee ,  Jae-Jin Lee

发明人： Kang-Seol Lee ,  Jae-Jin Lee

IPC分类号： G06F3/16

CPC分类号： G05F3/242 ,  G11C5/147 ,  G11C7/12

摘要： A voltage generator includes a bias signal generator generating first to fourth bias signals using a reference voltage, the first to fourth bias signals having different voltage levels. A driving signal generator receives the first and third bias signals to generate a pull-up signal in response to a voltage level of an output terminal and receiving the second and fourth bias signals to generate a pull-down signal in response to a voltage level of the output terminal. A voltage driver pulls up and pulls down a voltage level of the output terminal in response to the respective pull-up and pull-down signals. An auxiliary driving controller disables the pull-up signal when the voltage level of the output terminal is greater than that of the reference voltage and the pull-down signal when the voltage level of the output terminal is less than that of the reference voltage.

摘要翻译： 电压发生器包括利用参考电压产生第一至第四偏置信号的偏置信号发生器，第一至第四偏置信号具有不同的电压电平。 驱动信号发生器接收第一和第三偏置信号以响应于输出端的电压电平产生上拉信号，并且接收第二和第四偏置信号以响应于电压电平产生下拉信号 输出端子。 电压驱动器响应于相应的上拉和下拉信号而拉出并拉低输出端子的电压电平。 当输出端子的电压电平小于参考电压的电平时，辅助驱动控制器在输出端子的电压电平大于参考电压的电压电平和下拉信号时，禁用上拉信号。

公开(公告)号：US20080239838A1

公开(公告)日：2008-10-02

申请号：US12003548

申请日：2007-12-28

申请人： Sung-Soo Chi ,  Jae-Jin Lee

发明人： Sung-Soo Chi ,  Jae-Jin Lee

IPC分类号： G11C7/22 ,  G11C5/14

CPC分类号： G11C11/4085 ,  G11C8/08

摘要： A semiconductor memory device which includes: a voltage supplying unit for outputting a power source voltage as a driving source signal during a predetermined time, and then outputting a high voltage as the driving source signal in response to a driving control signal activated in response to an address signal; and a word line control unit for activating a word line at a voltage level of the driving source signal in response to the driving control signal.

摘要翻译： 一种半导体存储器件，包括：电压提供单元，用于在预定时间期间输出作为驱动源信号的电源电压，然后响应于响应于所述驱动源信号而被激活的驱动控制信号输出高电压作为驱动源信号 地址信号 以及字线控制单元，用于响应于驱动控制信号而在驱动源信号的电压电平下激活字线。

公开(公告)号：US20080129373A1

公开(公告)日：2008-06-05

申请号：US12027089

申请日：2008-02-06

申请人： Kang-Seol LEE ,  Jae-Jin Lee

发明人： Kang-Seol LEE ,  Jae-Jin Lee

IPC分类号： G05F3/02

CPC分类号： G11C5/145

摘要： The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

摘要翻译： 本发明提供了一种内部电压提供内部操作所需的最佳驾驶性能的电压供应器。 半导体存储器件的电压供应器包括：内部电压检测装置，用于检测内部电压的电压电平; 时钟振荡装置，用于输出电荷泵送时钟信号; 内部电压控制装置，用于根据数据访问模式或非数据访问模式选择性地控制时钟振荡装置; 以及电荷泵送装置，用于响应于电荷泵送时钟信号，通过泵送电荷来输出内部操作所需的内部电压。

公开(公告)号：US20070069710A1

公开(公告)日：2007-03-29

申请号：US11529255

申请日：2006-09-29

申请人： Kang-Seol Lee ,  Jae-Jin Lee

发明人： Kang-Seol Lee ,  Jae-Jin Lee

IPC分类号： G05F3/16

CPC分类号： G05F3/242 ,  G11C5/147 ,  G11C7/12

摘要： A voltage generator includes a bias signal generator generating first to fourth bias signals using a reference voltage, the first to fourth bias signals having different voltage levels. A driving signal generator receives the first and third bias signals to generate a pull-up signal in response to a voltage level of an output terminal and receiving the second and fourth bias signals to generate a pull-down signal in response to a voltage level of the output terminal. A voltage driver pulls up and pulls down a voltage level of the output terminal in response to the respective pull-up and pull-down signals. An auxiliary driving controller disables the pull-up signal when the voltage level of the output terminal is greater than that of the reference voltage and the pull-down signal when the voltage level of the output terminal is less than that of the reference voltage.

摘要翻译： 电压发生器包括利用参考电压产生第一至第四偏置信号的偏置信号发生器，第一至第四偏置信号具有不同的电压电平。 驱动信号发生器接收第一和第三偏置信号以响应于输出端的电压电平产生上拉信号，并且接收第二和第四偏置信号以响应于电压电平产生下拉信号 输出端子。 电压驱动器响应于相应的上拉和下拉信号而拉出并拉低输出端子的电压电平。 当输出端子的电压电平小于参考电压的电平时，辅助驱动控制器在输出端子的电压电平大于参考电压的电压电平和下拉信号时，禁止上拉信号。

公开(公告)号：US20060244518A1

公开(公告)日：2006-11-02

申请号：US11321873

申请日：2005-12-30

申请人： Sang-Jin Byeon ,  Jae-Jin Lee

发明人： Sang-Jin Byeon ,  Jae-Jin Lee

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： The present invention provides an internal voltage generator including a high efficient charge pump. The internal voltage generator includes an oscillation signal generator for receiving a reference voltage and a pumping voltage to thereby output an oscillation signal, a pump control logic for outputting a pumping control signal and a precharge signal in response to the oscillation signal, and a charge pump for precharging the pair of bootstrapping node by connecting the pair of bootstrapping node in response to the precharge signal to thereby generate the pumping voltage of a predetermined level after precharging the pair of bootstrapping node into a level of the power supply voltage and charge sharing the pair of bootstrapping node and the pumping voltage in response to the precharge signal. Herein, the pumping control signal controls a pumping operation and the precharge signal precharges a pair of bootstrapping node for generating the pumping voltage by pumping a power supply voltage.

摘要翻译： 本发明提供一种包括高效电荷泵的内部电压发生器。 内部电压发生器包括用于接收参考电压和泵浦电压从而输出振荡信号的振荡信号发生器，用于响应于振荡信号输出泵控制信号和预充电信号的泵控制逻辑，以及电荷泵 用于通过响应于预充电信号连接一对自举节点来预充电一对自举节点，从而在将一对自举节点预充电到电源电压的电平和电荷共享对之后产生预定电平的泵浦电压 的自举节点和响应于预充电信号的抽运电压。 这里，泵送控制信号控制泵送操作，并且预充电信号通过泵送电源电压来预充电一对自举节点以产生泵送电压。