公开(公告)号：US06268633B1

公开(公告)日：2001-07-31

申请号：US09222568

申请日：1998-12-28

申请人： Federico Pio ,  Olivier Pizzuto

发明人： Federico Pio ,  Olivier Pizzuto

IPC分类号： H01L2976

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

摘要翻译： 集成在具有第一类型导电性的半导体衬底中的电子器件的结构，其包括至少第一HV晶体管和至少第二LV晶体管，每个具有相应的栅极区域。 所述第一HV晶体管具有具有第二类型导电性的轻掺杂漏极和源极区，并且所述第二LV晶体管具有具有第二类型导电性的各自的漏极和源极区，每个包含与相应栅极区相邻的轻掺杂部分， 第二部分是更重掺杂的并且包括硅化物层。

公开(公告)号：US06215688B1

公开(公告)日：2001-04-10

申请号：US09364766

申请日：1999-07-30

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.

公开(公告)号：US5894146A

公开(公告)日：1999-04-13

申请号：US607067

申请日：1996-02-26

申请人： Federico Pio ,  Paola Paruzzi

发明人： Federico Pio ,  Paola Paruzzi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A matrix of EEPROM memory cells having a double polysilicon level of MOS technology and being arranged into rows and columns is monolithically integrated on a substrate of semiconductor material. Each cell comprises, in series, a transistor of the floating gate type which includes two layers of polysilicon superposed on each other and separated by an intervening layer of a dielectric material, and a selection transistor having a gate which comprises a first layer of polysilicon. The gates of the selection transistors in one row of said matrix are connected electrically together by a selection line comprising a second layer of polysilicon overlying the first layer. The intermediate layer of dielectric material is also partly interposed between the first and second layers of polysilicon such that the two layers are in contact at at least one zone of said selection line. Preferably, the contact zone is formed over field oxide regions and is away from the edges of the selection line. The matrix can advantageously be fabricated by a process of the self-aligned type, without making the process any more complicated.

摘要翻译： 具有MOS技术的双重多晶硅级别并被布置成行和列的EEPROM存储单元的矩阵被单片地集成在半导体材料的衬底上。 每个单元串联包括浮置型晶体管，该晶体管包括彼此重叠并由介电材料的中间层隔开的两层多晶硅，以及选择晶体管，其具有包括第一多晶硅层的栅极。 所述矩阵的一行中的选择晶体管的栅极通过包括覆盖在第一层上的第二多晶硅层的选择线电连接。 电介质材料的中间层也部分插入第一和第二多晶硅层之间，使得两层在所述选择线的至少一个区域处接触。 优选地，接触区形成在场氧化物区域上并远离选择线的边缘。 该矩阵可以有利地通过自对准型的工艺制造，而不会使工艺变得更加复杂。

公开(公告)号：US08841649B2

公开(公告)日：2014-09-23

申请号：US13600699

申请日：2012-08-31

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L45/06 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/101 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

摘要： Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

摘要翻译： 提供三维记忆阵列及其形成方法。 示例性三维存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部，使得 至少一个导电延伸部与多个第一导线中的至少一个的一部分相交。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。

公开(公告)号：US08737138B2

公开(公告)日：2014-05-27

申请号：US12949728

申请日：2010-11-18

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： G11C16/04 ,  G11C16/06 ,  G06F13/00

CPC分类号： G11C5/147 ,  G06F12/0246 ,  G06F21/60 ,  G06F2212/7204 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0063 ,  G11C14/009 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/107 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

摘要： Subject matter disclosed herein relates to techniques to operate memory.

摘要翻译： 本文公开的主题涉及操作存储器的技术。

公开(公告)号：US08406060B2

公开(公告)日：2013-03-26

申请号：US12949728

申请日：2010-11-18

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： G11C16/04 ,  G11C16/06 ,  G06F13/00

摘要： Subject matter disclosed herein relates to techniques to operate memory.

公开(公告)号：US08361833B2

公开(公告)日：2013-01-29

申请号：US12951304

申请日：2010-11-22

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： H01L21/00

CPC分类号： H01L45/1286 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16 ,  H01L45/1675

摘要： A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.

摘要翻译： 用于相变存储器的基本上平面的加热器可以向上延伸以逐渐接触硫族化物层。 结果，加热器和硫族化物之间的接触面积减小了。 在一些实施例中，这种减小的接触面积可以降低功耗。

公开(公告)号：US06815328B2

公开(公告)日：2004-11-09

申请号：US10001625

申请日：2001-10-24

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： H01L214763

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated device comprises a first conductive region and a first insulating region of dielectric material covering the first conductive region. A first through region of electrically conductive material extends inside the first insulating region, and is in direct electrical contact with the first conductive region. A second conductive region, arranged above the first insulating region, is in a position not aligned and not in contact with the first through region. A second insulating region of dielectric material covers the second conductive region. A second through region of electrically conductive material extends inside the second insulating region as far as the first through region and is aligned and in direct electrical contact with the first through region. A third conductive region, arranged above the second insulating region, is aligned and in direct electrical contact with the second through region.

公开(公告)号：US06677206B2

公开(公告)日：2004-01-13

申请号：US09740407

申请日：2000-12-19

申请人： Matteo Patelmo ,  Federico Pio

发明人： Matteo Patelmo ,  Federico Pio

IPC分类号： H01L21336

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

摘要翻译： 一种包括多个存储单元的非易失性存储器件，每个存储单元形成为具有源区域的MOS晶体管，漏极区域和具有与其形成侧面的栅极; 以及设置在栅极侧面上的一个或多个电介质间隔物。 至少一个存储单元被定义为ON状态，并且至少一个存储单元被定义为OFF状态。 处于导通状态的存储单元包括漏极区域和轻扩散漏极（LDD）类型的源极区域，其特征在于，处于断开状态的存储器单元的至少一个漏极区域和至少一个源极区域由 一个或多个高掺杂剂区域。 处于OFF状态的存储单元由定义为源极区域，漏极区域和栅极的一个或多个有源区域的顶部上的硅化物层组成。

公开(公告)号：US06643184B2

公开(公告)日：2003-11-04

申请号：US10057767

申请日：2002-01-24

申请人： Federico Pio

发明人： Federico Pio

IPC分类号： G11C1604

CPC分类号： G11C16/16

摘要： A method of erasing a flash memory integrated in a chip of semiconductor material and including at least one matrix of cells with a plurality of rows and a plurality of columns made in at least one insulated body, the cells of each row being connected to a corresponding word line; the method includes the step of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.