公开(公告)号：US08749293B2

公开(公告)日：2014-06-10

申请号：US13529557

申请日：2012-06-21

申请人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

发明人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

IPC分类号： G06G7/19 ,  H01L29/00

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

摘要翻译： 一种包括第一节点和第二节点的可编程无源设备。 电耦合到第一节点的多个无源器件元件。 多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

公开(公告)号：US20130314119A1

公开(公告)日：2013-11-28

申请号：US13478137

申请日：2012-05-23

申请人： Fen Chen ,  Kai Di Feng ,  Pui Ling Yee

发明人： Fen Chen ,  Kai Di Feng ,  Pui Ling Yee

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/00 ,  H01L2924/0002

摘要： A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.

摘要翻译： 公开了一种用于半导体结构的金属 - 金属泄漏和击穿测试结构以及使用该测试结构的方法。 测试结构包括连接到相应的两个终端设备的多个电阻桥。 测试结构还包括多个开关，每个开关具有设置在多个电阻器桥中的相应一个的电阻器之间的电压节点。 当多个开关中的相应一个开关处于导通状态时，在电路板处读取电压节点。 测试结构还包括单独地打开和关闭多个开关中的每一个的装置。

公开(公告)号：US08569888B2

公开(公告)日：2013-10-29

申请号：US13114079

申请日：2011-05-24

申请人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

发明人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

摘要翻译： 公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。 较厚的上部位于布线结构和相邻电介质材料之间的接合处。 较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。 较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

公开(公告)号：US20130038334A1

公开(公告)日：2013-02-14

申请号：US13207485

申请日：2011-08-11

申请人： David G. Brochu, JR. ,  Fen Chen ,  Roger A. Dufresne ,  Travis S. Merrill ,  Michael A. Shinosky

发明人： David G. Brochu, JR. ,  Fen Chen ,  Roger A. Dufresne ,  Travis S. Merrill ,  Michael A. Shinosky

IPC分类号： G01R31/02

CPC分类号： G01R31/2858

摘要： Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.

摘要翻译： 用于同时测试电迁移或应力迁移的测试结构在集成电路中的时间依赖介质击穿失效，使用布置为桥接平衡电路的四个测试结构的测试电路和使用测试电路的测试方法。 测试结构的电迁移或应力迁移部分包括通过导电通孔串联连接的导线段的通孔链，形成在集成电路的至少两个相邻布线层中的线段。 测试结构的时间依赖介质击穿部分包括在与数字化的线结构相同的布线级别中与所述线段的少于整个部分相邻的所述至少两个相邻布线层之一中的数字化线结构。

公开(公告)号：US20120261724A1

公开(公告)日：2012-10-18

申请号：US13529557

申请日：2012-06-21

申请人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

发明人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

IPC分类号： H01L23/52 ,  H01L21/326

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

摘要翻译： 一种包括第一节点和第二节点的可编程无源设备。 电耦合到第一节点的多个无源器件元件。 多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

公开(公告)号：US07842318B2

公开(公告)日：2010-11-30

申请号：US11907854

申请日：2007-10-18

申请人： Feng-Nien Ko ,  Mo-Chi Cheng ,  Cheng-Ko Liu ,  Jen-Wei Chen ,  Fen Chen ,  Chao-Chi Yei

发明人： Feng-Nien Ko ,  Mo-Chi Cheng ,  Cheng-Ko Liu ,  Jen-Wei Chen ,  Fen Chen ,  Chao-Chi Yei

IPC分类号： A61K36/9068

CPC分类号： A61K36/9068

摘要： The present invention discloses a new use of a potent product extracted from rhizomes of Zingiber officinale in treating a disease associated with Helicobacter pylori such as gastritis, gastric ulcer or duodenal ulcer in a patient. The potent product is prepared by a process including the steps of a) preparing a crude extract from rhizomes of Zingiber officinale, said crude extract comprising 6-gingerol and 6-shogaol; b) introducing the crude extract to a reverse phase chromatography column, and eluting the column with a first eluent having a polarity lower than water to obtain a first potent fraction or a second eluent having a polarity lower than that of the first eluent to obtain a second potent fraction. Preferably, the second potent fraction is substantially free of both 6-gingerol and 6-shogaol.

摘要翻译： 本发明公开了一种从姜黄根提取的有效产品在治疗与幽门螺杆菌相关的疾病如胃炎，胃溃疡或十二指肠溃疡中的新用途。 所述有效产物通过以下步骤制备，所述方法包括以下步骤：a）从姜黄根茎制备粗提取物，所述粗提物包含6-姜醇和6-shogaol; b）将粗提取物引入反相层析柱，并用极性低于水的第一洗脱液洗脱柱，以获得极性低于第一洗脱液的第一有效级分或第二洗脱液，从而获得 第二有效分数。 优选地，第二有效级分基本上不含6-姜醇和6-shogaol。

公开(公告)号：US20100133691A1

公开(公告)日：2010-06-03

申请号：US12698189

申请日：2010-02-02

申请人： Fen Chen ,  Cathryn Jeanne Christiansen ,  Michael Anthony Shinosky ,  Timothy Dooling Sullivan

发明人： Fen Chen ,  Cathryn Jeanne Christiansen ,  Michael Anthony Shinosky ,  Timothy Dooling Sullivan

IPC分类号： H01L23/50

CPC分类号： H01L21/76895 ,  H01L23/34 ,  H01L23/522 ,  H01L23/576 ,  H01L2924/0002 ,  Y10S438/917 ,  H01L2924/00

摘要： An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

摘要翻译： 互连和互连方法。 该方法包括在基底上形成电介质层，介电层具有顶表面和底表面; 在所述电介质层中形成第一线和第二线，所述第一线与所述第二线分离，通过所述介电层的区域; 并且在第一和第二布线之间的电介质层的顶表面中或上方形成金属纳米颗粒，仅在将纳米颗粒加热到大于室温的温度时能够电连接第一布线和第二布线的金属纳米颗粒， 在第一和第二导线之间施加电压。

公开(公告)号：US07500208B2

公开(公告)日：2009-03-03

申请号：US11673369

申请日：2007-02-09

申请人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

发明人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

IPC分类号： G06F17/50 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有部分的电阻来确定第一行几何调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

公开(公告)号：US08178434B2

公开(公告)日：2012-05-15

申请号：US13244998

申请日：2011-09-26

申请人： Fen Chen ,  Jeffrey P. Gambino ,  Alvin W. Strong

发明人： Fen Chen ,  Jeffrey P. Gambino ,  Alvin W. Strong

IPC分类号： H01L21/768

CPC分类号： H01L23/585 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

摘要翻译： 一种装置包括半导体芯片内的第一层，其具有与其它有源结构电连接并且具有电隔离的第一无效结构的有源结构。 半导体芯片内的第二层物理连接到第一层。 第二层包括绝缘体并具有第二非活性结构。 第一非活性结构与第二非活性结构物理对准。

公开(公告)号：US20120080771A1

公开(公告)日：2012-04-05

申请号：US12898340

申请日：2010-10-05

申请人： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

发明人： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

IPC分类号： H01L27/08 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L21/76805 ,  H01L25/0657 ,  H01L28/91 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

摘要翻译： 本发明提供一种3D通孔电容器及其形成方法。 电容器包括在基板上的绝缘层。 绝缘层具有通孔，其具有侧壁和底部。 第一电极覆盖通孔的侧壁和底部的至少一部分。 第一高k电介质材料层覆盖在第一电极上。 第一导电板在第一高k电介质材料层之上。 第二高k电介质材料层覆盖在第一导电板上并留下未填充的通孔的剩余部分。 在通孔的剩余部分中形成第二电极。 第一导电板基本上平行于第一电极并且不与第一和第二电极接触。 还提供了这种3D通孔电容器的阵列。