公开(公告)号：US5804497A

公开(公告)日：1998-09-08

申请号：US695101

申请日：1996-08-07

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Fred N. Hause

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Fred N. Hause

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/70

CPC分类号： H01L29/66537 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A selectively doped MOS transistor channel includes a deep impurity distribution and shallow impurity distribution. The deep impurity distribution is formed within high energy implant with an impurity of conductivity type opposite to the conductivity type of the source/drain regions of the transistor. In the n-channel regions, the deep impurity distribution preferably includes boron ions. The deep impurity distribution acts as a channel stop such that adjacent source/drain regions of the like type transistors are not inadvertently coupled during circuit operation. The shallow impurity distribution acts as a threshold implant by precisely controlling the doping of the transistor channel in the vicinity of the silicon oxide interface. The peak concentration of the shallow impurity distribution is located at a depth below the silicon surface which is greater than a depth typically associated with a threshold adjust implant. Because the impurity concentration of the shallow impurity distribution drops off rapidly from the peak concentration value, the concentration at the upper surface of the silicon substrate is not significantly greater than the doping of the silicon substrate itself. The light doping in the channel region of the transistor results in a substantially reduced threshold voltage for the transistor. Preferably, the threshold voltage of both the n-channel and p-channel devices has an absolute value of approximately 250 Mv. The lower threshold voltage translates into a higher I.sub.Dsat when the transistor is operated under normal conditions (e.g., V.sub.Gs =3 volts, V.sub.Ds =3 volts, and V.sub.sb =0 volts.)

摘要翻译： 选择掺杂的MOS晶体管沟道包括深杂质分布和浅杂质分布。 深度杂质分布形成在高能量注入内，其杂质的导电类型与晶体管的源/漏区的导电类型相反。 在n沟道区域中，深杂质分布优选包括硼离子。 深杂质分布充当通道阻挡，使得类似晶体管的相邻源极/漏极区在电路操作期间不会无意中耦合。 通过精确地控制在氧化硅界面附近的晶体管沟道的掺杂，浅杂质分布充当阈值注入。 浅杂质分布的峰值浓度位于硅表面下方的深度，该深度大于通常与阈值调整植入物相关联的深度。 由于浅杂质分布的杂质浓度从峰值浓度值迅速下降，所以硅衬底上表面的浓度不会明显大于硅衬底本身的掺杂。 在晶体管的沟道区域中的轻掺杂导致晶体管的阈值电压显着降低。 优选地，n沟道和p沟道器件的阈值电压具有约250Mv的绝对值。 当晶体管在正常条件下操作时（例如，VGs = 3V，VDs = 3V，Vsb = 0V），较低的阈值电压转换为更高的IDat。

公开(公告)号：US6083846A

公开(公告)日：2000-07-04

申请号：US65508

申请日：1998-04-24

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Fred N. Hause

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Fred N. Hause

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/90

摘要： A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a lateral surface to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. Preferably, the multi-layer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The oxide is grown upon the polysilicon to align a source/drain implant. Either before the source/drain implant or after the source/drain implant, the oxide and polysilicon partially consumed by the oxide is removed to provide a lateral surface to which an MDD implant aligns. A combination of etch stop, polysilicon spacer and grown possibly sacrificial oxide allows a greater ease by which multiple implants can be forwarded into junctions of either an NMOS or PMOS transistor.

摘要翻译： 提出了一种晶体管和晶体管制造方法，其中形成一系列层，并且在栅极导体的侧壁表面上完全或部分地去除层。 层的形成和去除产生可以对齐各种植入物的侧表面。 连续放置的那些植入物产生具有相对平滑的掺杂分布的高度梯度的结。 优选地，多层间隔结构包括插入在生长的氧化物和蚀刻停止点之间的多晶硅间隔物。 氧化物在多晶硅上生长以对准源极/漏极植入物。 在源极/漏极注入之前或源极/漏极注入之后，去除部分被氧化物消耗的氧化物和多晶硅以提供MDD植入物对准的侧表面。 蚀刻停止，多晶硅间隔物和生长的可能的牺牲氧化物的组合允许更大的容易性，通过该容易，多个注入可以被转发到NMOS或PMOS晶体管的结。

公开(公告)号：US6063679A

公开(公告)日：2000-05-16

申请号：US987558

申请日：1997-12-09

申请人： Mark I. Gardner ,  Fred N. Hause ,  Charles E. May

发明人： Mark I. Gardner ,  Fred N. Hause ,  Charles E. May

IPC分类号： H01L21/266 ,  H01L21/336

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L29/6659

摘要： The formation of a spacer for a graded dopant profile having a triangular geometry is disclosed. In one embodiment, a method has three steps. In the first step, a gate is formed on a substrate, the gate having two edges. In the second step, at least one spacer is formed, where each spacer is adjacent to an edge of the gate and has a triangular geometry. In the third step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer.

摘要翻译： 公开了用于具有三角形几何形状的渐变掺杂剂分布的间隔物的形成。 在一个实施例中，方法具有三个步骤。 在第一步骤中，栅极形成在衬底上，栅极具有两个边缘。 在第二步骤中，形成至少一个间隔件，其中每个间隔件邻近门的边缘并具有三角形几何形状。 在第三步骤中，施加离子注入以在每个间隔物下面的衬底内形成渐变的轻掺杂区域，该区域对应于间隔物的三角形几何形状。

公开(公告)号：US06046089A

公开(公告)日：2000-04-04

申请号：US2727

申请日：1998-01-05

申请人： Mark I. Gardner ,  Fred N. Hause ,  Charles E. May

发明人： Mark I. Gardner ,  Fred N. Hause ,  Charles E. May

IPC分类号： H01L21/311 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/31116

摘要： The formation of selectively sized spacers is disclosed. One embodiment comprises a method including four steps. In the first step, at least one spacer for each of a plurality of gates is formed on a substrate, the plurality of gates including a first gate and at least one remaining gate, and each spacer adjacent to an edge of its corresponding gate. In the second step, a mask is applied to the first gate, including the spacers for the first gate. In the third step, the spacers for the remaining gates are etched. In the fourth step, the mask applied to the first gate, including the spacers for the first gate, is removed.

摘要翻译： 公开了选择性尺寸的间隔物的形成。 一个实施例包括一个包括四个步骤的方法。 在第一步骤中，在衬底上形成用于多个栅极中的每一个的至少一个间隔物，所述多个栅极包括第一栅极和至少一个剩余栅极，并且每个间隔物邻近其对应栅极的边缘。 在第二步骤中，将掩模施加到第一栅极，包括用于第一栅极的间隔物。 在第三步骤中，蚀刻用于剩余栅极的间隔物。 在第四步骤中，去除了包括用于第一栅极的间隔物的第一栅极的掩模。

公开(公告)号：US5994779A

公开(公告)日：1999-11-30

申请号：US850253

申请日：1997-05-02

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Fred N. Hause

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Fred N. Hause

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76885 ,  H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002

摘要： An integrated circuit fabrication process is provided in which an interconnect having a least one vertical sidewall surface is formed. The interconnect thusly formed allows for higher packing density within the ensuring integrated circuit since the interconnect requires less space to accommodate the same current density as an interconnect having sloped (i.e., non-vertical) sidewall surfaces. A semiconductor topography is provided which includes transistors arranged upon and within a silicon-based substrate. A first interlevel dielectric is deposited across the semiconductor topography, and portions of the dielectric are removed to form vias to select portions of the transistors. Conductive plugs are formed exclusively within the vias. An insulating material patterned with vertical sidewall surfaces is then formed across the first interlevel dielectric and a portion of the plugs. The insulating material is then patterned. Conductive material is then deposited across the patterned insulating material, the plug upper surfaces, and the first interlevel dielectric. A portion of the conductive material is anisotropically removed to form interconnects which are laterally adjacent to the sidewall surfaces of the insulating material. Each interconnect includes two surfaces, one of which is vertical to the underlying topography and the other of which extends a distance from the fist surface and links with an upper region of the surface in an arcuate pattern. The first lateral surface of the interconnect is directly adjacent to a sidewall surface of the insulating material and is therefore intended to be vertical. The second lateral surface extends a distance from the first lateral surface, constrained the limitations of deposition and not lithography.

摘要翻译： 提供一种集成电路制造工艺，其中形成具有至少一个垂直侧壁表面的互连。 这样形成的互连允许在确保集成电路内的更高的封装密度，因为互连需要更少的空间以适应与具有倾斜（即，非垂直）侧壁表面的互连件相同的电流密度。 提供半导体形貌，其包括布置在硅基衬底上和内部的晶体管。 第一层间电介质淀积跨半导体形貌，去除电介质的部分以形成通孔以选择晶体管的部分。 导电插头仅在通孔内形成。 然后，跨越第一层间电介质和一部分插塞形成图案化有垂直侧壁表面的绝缘材料。 然后将绝缘材料图案化。 导电材料然后沉积在图案化的绝缘材料，插塞上表面和第一层间电介质上。 导电材料的一部分被各向异性地去除以形成横向邻近绝缘材料的侧壁表面的互连。 每个互连包括两个表面，其中一个垂直于下面的地形，另一个表面与第一表面延伸一段距离，并以弓形图案与表面的上部区域连接。 互连的第一侧表面直接邻近绝缘材料的侧壁表面，因此意图是垂直的。 第二侧表面从第一侧表面延伸一段距离，限制了沉积的限制，而不是光刻。

公开(公告)号：US5989964A

公开(公告)日：1999-11-23

申请号：US818427

申请日：1997-03-17

申请人： Mark I. Gardner ,  Fred N. Hause

发明人： Mark I. Gardner ,  Fred N. Hause

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  G01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/266

摘要： Broadly speaking, the present invention contemplates a semiconductor manufacturing process in which LDD regions of a semiconductor transistor are implanted after the heavily doped regions without requiring the removal of spacer structures from the sidewalls of the transistor gate. A semiconductor substrate is provided. The semiconductor substrate includes a channel region laterally displaced between first and second lightly doped regions. The first and second lightly doped regions are laterally displaced between first and second heavily doped regions of the semiconductor substrate. A gate dielectric is formed on an upper surface of the semiconductor substrate. A conductive gate structure is then formed on the gate dielectric. The conductive gate structure is aligned over the channel region of the semiconductor substrate. First and second spacer structures are then formed on first and second sidewalls of the conductive gate. The first and second spacer structures extend laterally from the first and second sidewalls of the conductive gate such that the first and second spacer structures cover the first and second lightly doped regions of the semiconductor substrate. A projected range characteristic of the first and second spacer structures is greater than a projected range characteristic of the conductive gate structures. A first impurity distribution is then introduced into the semiconductor substrate. An interlevel dielectric layer is then deposited on the underlying topography and planarized. A projected range characteristic of the interlevel dielectric layer is approximately equal to a projected range characteristic of the first and second spacer structures. A second impurity distribution is then implanted into the semiconductor substrate through the interlevel dielectric layer.

摘要翻译： 一般而言，本发明考虑了一种半导体制造工艺，其中在重掺杂区域之后注入半导体晶体管的LDD区域，而不需要从晶体管栅极的侧壁去除间隔结构。 提供半导体衬底。 半导体衬底包括在第一和第二轻掺杂区域之间横向移位的沟道区域。 第一和第二轻掺杂区域在半导体衬底的第一和第二重掺杂区域之间横向移位。 栅电介质形成在半导体衬底的上表面上。 然后在栅极电介质上形成导电栅极结构。 导电栅极结构在半导体衬底的沟道区上对准。 然后在导电栅极的第一和第二侧壁上形成第一和第二间隔结构。 第一和第二间隔结构从导电栅极的第一和第二侧壁横向延伸，使得第一和第二间隔结构覆盖半导体衬底的第一和第二轻掺杂区域。 第一和第二间隔结构的投影范围特性大于导电栅结构的投影范围特性。 然后将第一杂质分布引入半导体衬底。 然后将层间电介质层沉积在下面的地形上并且被平坦化。 层间电介质层的投影范围特性近似等于第一和第二间隔结构的投影范围特性。 然后通过层间电介质层将第二杂质分布注入到半导体衬底中。

公开(公告)号：US5962914A

公开(公告)日：1999-10-05

申请号：US168761

申请日：1998-10-08

申请人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

发明人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

IPC分类号： H01L21/762 ,  H01L24/36

CPC分类号： H01L21/76213

摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

公开(公告)号：US5937310A

公开(公告)日：1999-08-10

申请号：US639758

申请日：1996-04-29

申请人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

发明人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76213 ,  Y10S438/981

摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

摘要翻译： 在不使用氮化硅的情况下形成自对准场氧化物隔离结构的方法。 该方法包括在半导体衬底的上表面上形成电介质。 半导体衬底的上表面包括相互横向相邻的有源区和隔离区。 在植入电介质的顶部上构图光致抗蚀剂层，以在有源区域上暴露植入电介质的区域。 然后通过植入电介质将氮注入有源区。 氮优选以0.5至2.0％的近似原子浓度引入半导体衬底。 在将氮气注入到半导体衬底中之后，剥离光致抗蚀剂层并除去注入电介质。 然后将晶片热氧化，使得具有第一厚度的场氧化物在隔离区上生长，并且在有源区上生长具有第二厚度的薄氧化物。 半导体衬底内的氮的存在阻碍了有源区中硅的氧化速率，使得薄氧化物的厚度基本上小于热氧化物的厚度。 在目前优选的实施例中，场氧化物的厚度为2,000至8,000埃，而薄氧化物的厚度小于300埃。

公开(公告)号：US5926693A

公开(公告)日：1999-07-20

申请号：US788376

申请日：1997-01-27

申请人： Mark I. Gardner ,  Fred N. Hause ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Fred N. Hause ,  Jon D. Cheek

IPC分类号： H01L27/07 ,  H01L27/088 ,  H01L21/00

CPC分类号： H01L27/0705 ,  H01L27/088

摘要： A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth. The trench depth is preferably greater than a junction depth of the source/drain structures. In one embodiment, the formation of the trench transistor further includes, prior to the thermal oxidation of the trench floor, forming first and second ldd structures within the first and second trench ldd regions of the substrate. The first and second trench ldd structures provide conductive paths that extend from a trench channel region located beneath the trench floor to the first and the second shared source/drain structures respectively.

摘要翻译： 一种半导体工艺，其中沟槽晶体管形成在一对平面晶体管之间，使得沟槽晶体管的源极/漏极区域与平面晶体管的源极/漏极区域共享。 提供衬底，并且在衬底的上表面上形成第一和第二平面晶体管。 沟槽晶体管的栅极电介质在衬底的上表面下方垂直位移。 沟槽晶体管与第一平面晶体管共享第一共享源极/漏极结构，并且与第二平面晶体管共享第二共享源极/漏极结构。 沟槽晶体管的形成优选地包括以下步骤：将沟槽蚀刻到衬底中，热氧化沟槽的底部以形成沟槽栅极电介质，并用导电材料填充沟槽以形成沟槽栅极结构。 沟槽底部通过沟槽深度在衬底的上表面下方垂直移位。 沟槽深度优选地大于源极/漏极结构的结深度。 在一个实施例中，沟槽晶体管的形成还包括在沟槽底板的热氧化之前，在衬底的第一和第二沟槽区域内形成第一和第二层结构。 第一和第二沟槽层结构提供从位于沟槽底部下方的沟槽沟道区域分别延伸到第一和第二共享源极/漏极结构的导电路径。

公开(公告)号：US5849621A

公开(公告)日：1998-12-15

申请号：US666023

申请日：1996-06-19

申请人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  Fred N. Hause ,  H. Jim Fulford, Jr.

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/76

CPC分类号： H01L21/823418 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823481 ,  Y10S257/90

摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.

摘要翻译： 一种用于隔离半导体器件的方法，包括提供半导体衬底。 半导体衬底包括横向移位的源极/漏极区域和沟道区域。 第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。 第一和第二晶体管具有公共源极/漏极区域。 通过公共源极/漏极区域形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得公共源极/漏极区域被分成电隔离的第一和第二源极/漏极区域，由此第一晶体管与 第二晶体管。