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    Method for making high voltage integrated circuit devices in a fin-type process and resulting devices
    41.
    发明授权
    Method for making high voltage integrated circuit devices in a fin-type process and resulting devices 有权
    在鳍型工艺中制造高压集成电路器件的方法和所得器件

    公开(公告)号：US09520396B2

    公开(公告)日：2016-12-13

    申请号：US14965193

    申请日：2015-12-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar Singh

    IPC: H01L29/66 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/8234

    CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

    Abstract: Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.

    Abstract translation: 公开了利用鳍式工艺制造高压IC器件和所得器件的方法。 实施例包括在衬底层上形成由空间隔开的两个多个硅散热片，其中相邻的硅散热片被沟槽分开; 在衬底层上形成氧化物层并填充每个沟槽的一部分; 形成两个深的隔离沟槽到与两个多个硅散热片相邻的氧化物层和衬底层; 通过将掺杂剂注入到两个多个硅散热片下方的衬底层中来形成渐变电压结; 在所述氧化物层和所述两个硅散热片之间形成栅极结构; 将掺杂剂注入到两个多个硅散热片之中和之下，形成源区和漏区; 并在两个多个硅散热片上形成外延层以形成合并的源极和漏极散热片。

    Dual three-dimensional and RF semiconductor devices using local SOI
    42.
    发明授权
    Dual three-dimensional and RF semiconductor devices using local SOI 有权
    使用局部SOI的双重三维和RF半导体器件

    公开(公告)号：US09508743B2

    公开(公告)日：2016-11-29

    申请号：US14525842

    申请日：2014-10-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar Singh ,  Srikanth Balaji Samavedam

    IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L23/66 ,  H01L21/762 ,  H01L27/092

    CPC classification number: H01L27/1211 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/845 ,  H01L23/66 ,  H01L27/092 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Co-fabrication of a radio-frequency (RF) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created. The RF device(s) are fabricated on the layer of isolation material above the epitaxial material, which creates a local silicon-on-insulator, while the three-dimensional semiconductor device(s) can be fabricated on the raised structure(s).

    Abstract translation: 具有三维半导体器件的射频（RF）半导体器件的共同制造包括提供起始三维半导体结构，起始结构包括体硅半导体衬底，耦合到衬底的凸起半导体结构 并被一层隔离材料包围。 在相邻的凸起结构之间的隔离材料层的跨度是凹进的，并且在隔离材料的凹陷跨度上形成一层外延半导体材料，在其上产生另一层隔离材料。 RF器件制造在外延材料上方的隔离材料层上，其产生局部绝缘体上硅，而三维半导体器件可以在凸起结构上制造。

    SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS
    43.
    发明申请
    SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS 有权
    用于集成电路的分立零电压电压场效应晶体管

    公开(公告)号：US20150270400A1

    公开(公告)日：2015-09-24

    申请号：US14217691

    申请日：2014-03-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar Singh ,  Konstantin G. Korablev ,  Andy Chih-Hung Wei

    IPC: H01L29/78 ,  H01L21/265 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

    Abstract: Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).

    Abstract translation: 提供了用于改变鳍式场效应晶体管（FinFET）器件中的阈值电压（例如，零阈值电压）的方法。 在本发明的实施例中，在具有p阱构造的翅片衬底上形成第一N +区和第二N +区。 位于第一N +区域和第二N +区域之间的翅片式衬底的区域掺杂有负极植入物种以形成n阱。 考虑到衬底装置的现有p-阱结构来改变该n阱区的尺寸和/或组成以改变FinFET器件的阈值电压（例如，产生零阈值电压FinFET器件）。

    Polysilicon resistor formation
    44.
    发明授权
    Polysilicon resistor formation 有权
    多晶硅电阻器形成

    公开(公告)号：US08946039B2

    公开(公告)日：2015-02-03

    申请号：US13767930

    申请日：2013-02-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar Singh ,  Shesh Mani Pandey ,  Roderick Miller ,  Nam Sung Kim

    IPC: H01L21/8222 ,  H01L49/02

    CPC classification number: H01L28/20

    Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

    Abstract translation: 本发明的各方面涉及用单一注入剂量植入和形成多晶硅电阻器的方法。 具体地，在电阻表面上形成具有一组开口的掩模。 一组开口通常根据预定图案以列排布置形成。 以这种方式形成掩模允许电阻器表面具有多个区域/区域。 第一区域由掩模中的一组开口限定，第二区域由掩模的其余部分限定。 然后通过开口对电阻器进行单次注入剂量。 以这种方式植入电阻器，电阻器具有多个电阻值（即，第一区域中的第一电阻值，以及第二区域中的第二电阻值）。

    Insulating inductor conductors with air gap using energy evaporation material (EEM)
    47.
    发明授权
    Insulating inductor conductors with air gap using energy evaporation material (EEM) 有权

    公开(公告)号：US10832842B2

    公开(公告)日：2020-11-10

    申请号：US16550431

    申请日：2019-08-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sunil K. Singh ,  Jagar Singh

    IPC: H01F5/06 ,  H01F5/00 ,  H01F17/00 ,  H01L49/02

    Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

    SOI DEVICE STRUCTURES WITH DOPED REGIONS PROVIDING CHARGE SINKING
    48.
    发明申请
    SOI DEVICE STRUCTURES WITH DOPED REGIONS PROVIDING CHARGE SINKING 审中-公开

    公开(公告)号：US20200035785A1

    公开(公告)日：2020-01-30

    申请号：US16045267

    申请日：2018-07-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar Singh ,  Jerome Ciavatti ,  Jae Gon Lee ,  Josef Watts

    IPC: H01L29/06 ,  H01L21/762 ,  H01L21/265

    Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

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