公开(公告)号：US10170553B2

公开(公告)日：2019-01-01

申请号：US15626241

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/423 ,  H01L29/732 ,  H01L21/306 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L29/10

Abstract: Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.

公开(公告)号：US10153361B2

公开(公告)日：2018-12-11

申请号：US15360295

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. Camillo-Castillo ,  Vibhor Jain ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L29/737 ,  H01L21/8222 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L27/082 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H03F3/21

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.

公开(公告)号：US20180240897A1

公开(公告)日：2018-08-23

申请号：US15437168

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/7375 ,  H01L29/165 ,  H01L29/66242

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. The device structure further includes an emitter, an intrinsic base that has a first thickness, and an extrinsic base coupled with the intrinsic base. The extrinsic base has a lateral arrangement relative to the intrinsic base and relative to the emitter. The intrinsic base has a vertical arrangement between the emitter and the top surface of the collector. The sidewall of the collector extends laterally to undercut the extrinsic base. The extrinsic base has a second thickness that is greater than a first thickness of the intrinsic base.

公开(公告)号：US09899375B1

公开(公告)日：2018-02-20

申请号：US15226575

申请日：2016-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L29/737 ,  H01L27/082 ,  H01L23/66 ,  H01L29/165 ,  H01L21/8222 ,  H01L29/08 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/306 ,  H03F3/195 ,  H03F3/213

CPC classification number: H01L27/0823 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/8222 ,  H01L23/66 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/165 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/294

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to co-integration of self-aligned and non-self aligned heterojunction bipolar transistors and methods of manufacture. The structure includes at least two heterojunction bipolar transistor (HBT) devices integrated onto a same wafer with different epitaxial base profiles. An intrinsic base epitaxy for a second device of the at least two HBT devices acts as an extrinsic base for a first device of the at least two HBT devices.

公开(公告)号：US20180040611A1

公开(公告)日：2018-02-08

申请号：US15226575

申请日：2016-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L27/082 ,  H01L29/165 ,  H01L21/8222 ,  H03F3/213 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/306 ,  H03F3/195 ,  H01L23/66 ,  H01L29/08

CPC classification number: H01L27/0823 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/8222 ,  H01L23/66 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/165 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/294

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to co-integration of self-aligned and non-self aligned heterojunction bipolar transistors and methods of manufacture. The structure includes at least two heterojunction bipolar transistor (HBT) devices integrated onto a same wafer with different epitaxial base profiles. An intrinsic base epitaxy for a second device of the at least two HBT devices acts as an extrinsic base for a first device of the at least two HBT devices.

公开(公告)号：US09721949B1

公开(公告)日：2017-08-01

申请号：US15010189

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Qizhi Liu ,  David Harame ,  Renata Camillo-Castillo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/324 ,  H01L21/823821 ,  H01L21/823892

Abstract: A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

公开(公告)号：US20160064484A1

公开(公告)日：2016-03-03

申请号：US14476007

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： David L. Harame ,  Michael L. Kerbaugh ,  Qizhi Liu

IPC: H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/1004 ,  H01L21/84 ,  H01L27/12 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/66272 ,  H01L29/732

Abstract: Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors.

Abstract translation: 形成双极器件结构和双极器件结构的方法。 可以在绝缘体上硅衬底的器件层中形成开口，该器件层延伸到绝缘体上硅衬底的掩埋绝缘体层。 内部基极层可以通过在与开口相邻的器件层的相对的第一和第二侧壁上的横向生长而在器件层内生长。 器件结构的第一双极结型晶体管的第一集电极可以以与第一侧壁隔开的第一间隔形成。 器件结构的第二双极结晶体管的第二集电极可以形成在距离第二侧壁的第二间隔处。 在开口内形成由第一双极结型晶体管和第二双极晶体管共用的发射极。 本征基极层的一部分可以为第一和第二双极结型晶体管提供相应的本征基极。

公开(公告)号：US20190326411A1

公开(公告)日：2019-10-24

申请号：US15961364

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Pernell Dongmo ,  Cameron Luce ,  James W. Adkisson ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

公开(公告)号：US10439053B2

公开(公告)日：2019-10-08

申请号：US16394421

申请日：2019-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L27/12 ,  H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L21/84

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US10367084B2

公开(公告)日：2019-07-30

申请号：US15664418

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768 ,  H01L21/84 ,  H01L29/165

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.