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    Vertical field-effect transistors with controlled dimensions
    42.
    发明授权
    Vertical field-effect transistors with controlled dimensions 有权

    公开(公告)号：US10236363B2

    公开(公告)日：2019-03-19

    申请号：US15458457

    申请日：2017-03-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chun-chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

    IPC: H01L29/66 ,  H01L21/311 ,  H01L21/324 ,  H01L29/417 ,  H01L29/78 ,  H01L29/10

    Abstract: Device structures and fabrication methods for a vertical field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A first spacer layer is formed on the first source/drain region. A dielectric layer is formed that extends in the vertical direction from the first spacer layer to a top surface of the semiconductor fin. The dielectric layer is recessed in the vertical direction, and a second spacer layer is formed on the recessed dielectric layer such that the dielectric layer is located in the vertical direction between the first spacer layer and the second spacer layer. After the dielectric layer is removed to open a space between the first spacer layer and the second spacer layer, a gate electrode is formed in the space. The vertical field-effect transistor has a gate length that is equal to a thickness of the recessed dielectric layer.

    Controlling self-aligned gate length in vertical transistor replacement gate flow
    45.
    发明授权
    Controlling self-aligned gate length in vertical transistor replacement gate flow 有权

    公开(公告)号：US10199480B2

    公开(公告)日：2019-02-05

    申请号：US15280451

    申请日：2016-09-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Tenko Yamashita ,  Kangguo Cheng ,  Chun-Chen Yeh

    IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/033 ,  H01L27/088 ,  H01L29/417

    Abstract: A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an interface therebetween. The semiconductor structure further includes a top source/drain layer over the vertical channel, and a self-aligned contact to each of the top and bottom source/drain layer and the gate. The semiconductor structure can be realized by providing a semiconductor substrate with a bottom source/drain layer thereover, forming a vertical channel over the bottom source/drain layer, forming a dummy gate wrapped around the vertical channel, and forming a bottom spacer layer and a top spacer layer around a top portion and a bottom portion, respectively, of the vertical channel, a remaining center portion of the vertical channel defining a fixed vertical channel height. The method further includes forming a top source/drain layer over the vertical channel, replacing the dummy gate with a metal gate, and forming self-aligned source, drain and gate contacts.

    Forming a gate contact in the active area
    46.
    发明授权
    Forming a gate contact in the active area 有权

    公开(公告)号：US10170583B2

    公开(公告)日：2019-01-01

    申请号：US15244067

    申请日：2016-08-23

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

    Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.

    Vertical transistor having buried contact, and contacts using work function metals and silicides
    48.
    发明授权
    Vertical transistor having buried contact, and contacts using work function metals and silicides 有权

    公开(公告)号：US10103247B1

    公开(公告)日：2018-10-16

    申请号：US15785631

    申请日：2017-10-17

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/45 ,  H01L21/8234

    Abstract: Methods form a structure having a lower source/drain contacting a substrate at the bottom of a transistor. A semiconductor fin extends from the lower source/drain away from the bottom of the transistor. An upper source/drain contacts an opposite end of the fin at the top of the transistor. A gate conductor surrounds (but is electrically insulated from the fin) and includes a raised contact portion extending toward the top of the transistor. A buried contact is located at the bottom of the transistor, and is electrically connected to the first source/drain. A silicide and a conformal metal are between the buried contact and the first source/drain. The conformal metal is also between the gate conductor and the fin. A first contact extends to the buried contact, a second contact extends to the upper source/drain, and a third contact extends to the raised contact portion.

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