公开(公告)号：US06410985B1

公开(公告)日：2002-06-25

申请号：US09563958

申请日：2000-05-02

Applicant: Tsiu C. Chan ,  Anthony M. Chiu ,  Gregory C. Smith

Inventor： Tsiu C. Chan ,  Anthony M. Chiu ,  Gregory C. Smith

IPC: H01L2348

CPC classification number: H01L21/76873 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 &mgr;m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution. The filled groove which results does not exhibit voids ordinarily resulting from sputter deposition of metal into such narrow, deep grooves, although seams may be intermittently present in portions of the filled groove where metal plated from the opposing sidewalls did not fuse flawlessly at the point of convergence. Portions of the silver and other layers above the insulating material are then removed by chemical-mechanical polishing, leaving a silver interconnect connected to the exposed portion of the contact region and extending over adjacent insulating regions to another contact region or a bond pad. Silver interconnects thus formed may have smaller cross-sections, and thus a greater density in a given area, than conventional metallic interconnects.

Abstract translation: 通过在接触区域上将深槽蚀刻成绝缘层，暴露接触区域的部分并限定互连形成银互连。 凹槽被蚀刻成具有截顶的V形或U形，在顶部比在任何其它垂直位置处更宽，并且具有0.25μm或更小的最小宽度。 将可选的粘合层和阻挡层溅射到包括侧壁的凹槽的表面上，然后溅射沉积种子层。 当铝用作种子层时，可以任选地使用锌化工艺以促进银与种子层的粘附。 然后通过在银溶液中电镀银，或者通过在铜溶液中电镀银和铜，然后在银溶液中电镀来填充槽。 导致的填充凹槽通常不会由金属溅射沉积到这样窄的深沟槽中而产生空隙，尽管接缝可以间歇地存在于填充凹槽的部分中，其中从相对的侧壁电镀的金属在 收敛。 然后通过化学机械抛光去除绝缘材料上方的银和其它层的部分，留下连接到接触区域的暴露部分并在相邻绝缘区域上延伸到另一接触区域或接合焊盘的银互连。 如此形成的银互连可以具有比常规金属互连更小的横截面，并且因此在给定区域中具有更大的密度。

公开(公告)号：US6100194A

公开(公告)日：2000-08-08

申请号：US102431

申请日：1998-06-22

Applicant: Tsiu C. Chan ,  Anthony M. Chiu ,  Gregory C. Smith

Inventor： Tsiu C. Chan ,  Anthony M. Chiu ,  Gregory C. Smith

IPC: C23C18/31 ,  C25D3/46 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1089 ,  H01L2924/0002

Abstract: Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 .mu.m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution. The filled groove which results does not exhibit voids ordinarily resulting from sputter deposition of metal into such narrow, deep grooves, although seams may be intermittently present in portions of the filled groove where metal plated from the opposing sidewalls did not fuse flawlessly at the point of convergence. Portions of the silver and other layers above the insulating material are then removed by chemical-mechanical polishing, leaving a silver interconnect connected to the exposed portion of the contact region; and extending over adjacent insulating regions to another contact region or a bond pad. Silver interconnects thus formed may have smaller cross-sections, and thus a greater density in a given area, than conventional metallic interconnects.

Abstract translation: 通过在接触区域上将深槽蚀刻成绝缘层，暴露接触区域的部分并限定互连形成银互连。 蚀刻具有截断的V形或U形的凹槽，在顶部比在任何其它垂直位置处更宽，并且具有0.25μm或更小的最小宽度。 将可选的粘合层和阻挡层溅射到包括侧壁的凹槽的表面上，然后溅射沉积种子层。 当铝用作种子层时，可以任选地使用锌化工艺以促进银与种子层的粘附。 然后通过在银溶液中电镀银，或者通过在铜溶液中电镀银和铜，然后在银溶液中电镀来填充槽。 导致的填充凹槽通常不会由金属溅射沉积到这样窄的深沟槽中而产生空隙，尽管接缝可以间歇地存在于填充凹槽的部分中，其中从相对的侧壁电镀的金属在 收敛。 然后通过化学机械抛光去除绝缘材料上方的银和其它层的部分，留下连接到接触区域的暴露部分的银互连; 并且在相邻的绝缘区域上延伸到另一个接触区域或接合焊盘。 如此形成的银互连可以具有比常规金属互连更小的横截面，并且因此在给定区域中具有更大的密度。

公开(公告)号：US5683924A

公开(公告)日：1997-11-04

申请号：US486347

申请日：1995-06-07

Applicant: Tsiu C. Chan ,  Gregory C. Smith

Inventor： Tsiu C. Chan ,  Gregory C. Smith

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/6659 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/7833

Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a dielectric. LDD regions are formed in the substrate adjacent the transistors and the field oxide regions. Doped polysilicon raised source and drain regions are formed overlying the LDD regions and a tapered portion of the field oxide region and adjacent the transistor. These polysilicon raised source and drain regions will help to prevent any undesired amount of the substrate silicon from being consumed, reducing the possibility of junction leakage and punchthrough as well as providing a more planar surface for subsequent processing steps.

Abstract translation: 提供一种用于形成半导体集成电路的平面晶体管的方法和根据该集成电路形成的集成电路。 形成多个场氧化物区域，覆盖基板，电绝缘封装在电介质中的多个晶体管。 LDD区域形成在与晶体管和场氧化物区域相邻的衬底中。 掺杂的多晶硅凸起的源极和漏极区域形成为覆盖LDD区域和场氧化物区域的锥形部分并且与晶体管相邻。 这些多晶硅升高的源极和漏极区域将有助于防止任何不希望量的衬底硅被消耗，减少了结漏电和穿透的可能性，并且为随后的处理步骤提供了更平的表面。

公开(公告)号：USD378751S

公开(公告)日：1997-04-08

申请号：US45441

申请日：1995-10-19

Applicant: Gregory C. Smith

Designer： Gregory C. Smith

公开(公告)号：US5514129A

公开(公告)日：1996-05-07

申请号：US161737

申请日：1993-12-03

Applicant: Gregory C. Smith

Inventor： Gregory C. Smith

IPC: A61B18/12 ,  A61B18/14 ,  A61B17/39

CPC classification number: A61B18/1206 ,  A61B18/1402 ,  A61B2018/00666 ,  A61B2018/00672 ,  A61B2018/00678 ,  A61B2018/00702 ,  A61B2018/00708 ,  A61B2018/00827 ,  A61B2018/00875 ,  A61B2018/00892 ,  A61B2018/1273

Abstract: An automatic circuit measures electrosurgical generator output and controls in accord with impedance between activated movable bipolar electrodes able to contact tissue. Voltage monitor in parallel and current monitor in series with the electrodes measure instantaneous variations and generate proportional signals. First and second calculators receive the signals and find respectively, by dividing the voltage by current, short circuit impedances and impedances other than short circuit impedances between the electrodes. First and second comparators receive the respective outputs from the first and second calculators and assess them against respective first and second references providing signs of short conditions and assessments of changes in impedance between the electrodes. A logic analyzer receives the signs and assessments and evaluates them to permit the instantaneous starting, operating or stopping of the electrosurgical generator. The electrodes include an instrument and a set of cables with a preselected combined impedance so the maximum instantaneous impedance between the electrodes is less than the preselected combined impedance. The second reference is user adjustable. Switches, associated with each of the voltage monitor and the current monitor, choose the gain applied to the proportional signals respectively therefrom. First and second calculator gain changers receive the signals for setting the range across which those respective signals are used. Methods have steps of monitoring voltage and current, generating signals, dividing the voltage signal by current signal to find short circuit impedance between the electrodes and the instantaneous changes in impedance for other than the short circuit impedance, assessing those findings against references and permitting the starting, operating, or stopping of the electrosurgical generator.

Abstract translation: 自动电路根据能够接触组织的活化双极电极之间的阻抗来测量电外科发生器的输出和控制。 与电极串联的电压监视器与电极串联测量瞬时变化并产生比例信号。 第一和第二计算器通过将电压除以电压之间的电压，短路阻抗和电阻之间的短路阻抗以外的其他阻抗分别接收信号。 第一和第二比较器接收来自第一和第二计算器的各自的输出，并且针对相应的第一和第二参考来评估它们，提供短条件的迹象并评估电极之间的阻抗变化。 逻辑分析仪接收标志和评估，并对其进行评估，以允许电外科发生器的瞬时启动，操作或停止。 电极包括仪器和具有预选组合阻抗的一组电缆，因此电极之间的最大瞬时阻抗小于预选的组合阻抗。 第二个参考用户可调。 与电压监视器和电流监视器中的每一个相关联的开关分别选择应用于比例信号的增益。 第一和第二计算器增益变换器接收用于设定使用这些各个信号的范围的信号。 方法有步骤监测电压和电流，产生信号，通过电流信号划分电压信号，以找到电极之间的短路阻抗和除短路阻抗之外的瞬时阻抗变化，评估这些发现与参考并允许启动 ，操作或停止电外科发生器。

公开(公告)号：US5055423A

公开(公告)日：1991-10-08

申请号：US383304

申请日：1989-07-18

Applicant: Gregory C. Smith ,  Thomas D. Bonifield

Inventor： Gregory C. Smith ,  Thomas D. Bonifield

IPC: H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/32051 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76807

Abstract: In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

Abstract translation: 在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。 然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。 沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和 进入孔（20）。 此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面 第二电介质层（30）。

公开(公告)号：US5021920A

公开(公告)日：1991-06-04

申请号：US502461

申请日：1990-03-30

Applicant: Gregory C. Smith

Inventor： Gregory C. Smith

IPC: H01L21/02 ,  H01L21/334 ,  H01L27/108 ,  H01L29/92

CPC classification number: H01L27/10805 ,  H01L28/90 ,  H01L29/66181

Abstract: A multilevel capacitor includes a selected number of interleaved conductive layers alternately of first and second conductivity types, each separated by interleaved dielectric layers, forming multilevel capacitor plates. The multilevel capacitor plates include at least first and second contact-edge areas, each including adjacent edges of each interleaved conductive/dielectric layer.A first electrode of the first conductivity type contacts the first contact-edge area, and a second electrode of the second conductivity type contacts the second contact-edge area. That is, these electrodes contact the corresponding edges of the interleaved conductive/dielectric layers within respective contact-edge areas.When appropriate bias voltages are applied to the first and second electrodes, each electrode is conductively coupled to the interleaved conductive layers of the same conductivity type, and junction isolated from the interleaved conductive layers of the other conductivity type, thereby permitting alternate layers to be changed to alternate potentials.

Abstract translation: 多电容电容器包括交替的第一和第二导电类型的选择数量的交错导电层，每个由交错的电介质层隔开，形成多层电容器板。 多电容电容器板包括至少第一和第二接触边缘区域，每个包括每个交替的导电/介电层的相邻边缘。 第一导电类型的第一电极接触第一接触边缘区域，第二导电类型的第二电极接触第二接触边缘区域。 也就是说，这些电极在相应的接触边缘区域内接触交替的导电/介电层的相应边缘。 当适当的偏置电压施加到第一和第二电极时，每个电极与相同导电类型的交错导电层导电耦合，并且与另一导电类型的交错导电层隔离，从而允许交替的层被改变 交替潜力。

公开(公告)号：US4184536A

公开(公告)日：1980-01-22

申请号：US880254

申请日：1978-02-22

Applicant: Gregory C. Smith ,  Richard D. Tokarz ,  Harvey L. Parry, Jr. ,  Daniel J. Braun

Inventor： Gregory C. Smith ,  Richard D. Tokarz ,  Harvey L. Parry, Jr. ,  Daniel J. Braun

IPC: F28F25/00 ,  F28B1/06 ,  F28D5/00 ,  F28D21/00 ,  F28F27/00

CPC classification number: F28F1/04 ,  F28B1/02 ,  F28B1/06 ,  F28B9/06 ,  F28D7/0066 ,  F28F1/24 ,  Y10S165/90 ,  Y10S261/11

Abstract: A cooling system for rejecting waste heat consists of a cooling tower incorporating a plurality of coolant tubes provided with cooling fins and each having a plurality of cooling channels therein, means for directing a heat exchange fluid from the power plant through less than the total number of cooling channels to cool the heat exchange fluid under normal ambient temperature conditions, means for directing water through the remaining cooling channels whenever the ambient temperature rises above the temperature at which dry cooling of the heat exchange fluid is sufficient and means for cooling the water.

Abstract translation: 用于排除废热的冷却系统包括：冷却塔，其包括设置有冷却翅片的多个冷却剂管，每个冷却管具有多个冷却通道，用于将来自发电厂的热交换流体引导到少于 冷却通道以在正常环境温度条件下冷却热交换流体，每当环境温度升高到热交换流体的干燥冷却足够的温度和用于冷却水的装置的温度时，将水引导通过剩余的冷却通道的装置。