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    Performing complex multiply-accumulate operations
    44.
    发明授权
    Performing complex multiply-accumulate operations 有权

    公开(公告)号：US11507761B2

    公开(公告)日：2022-11-22

    申请号：US16072279

    申请日：2016-02-25

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Brent Buchanan ,  Le Zheng

    IPC: G11C7/10 ,  G06G7/163 ,  G05F3/26 ,  G06N3/063 ,  G11C11/54 ,  G11C13/00 ,  H01L43/08

    Abstract: In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.

    Memristive bit cell with switch regulating components
    45.
    发明授权
    Memristive bit cell with switch regulating components 有权

    公开(公告)号：US11158370B2

    公开(公告)日：2021-10-26

    申请号：US16065364

    申请日：2016-01-26

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Emmanuelle J. Merced Grafals ,  Brent Buchanan ,  Le Zheng

    IPC: G11C11/00 ,  G11C13/00

    Abstract: In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.

    Memristive arrays with a waveform generation device
    46.
    发明授权
    Memristive arrays with a waveform generation device 有权

    公开(公告)号：US10593403B2

    公开(公告)日：2020-03-17

    申请号：US16073902

    申请日：2016-02-23

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Brent Buchanan ,  Le Zheng

    IPC: G11C11/00 ,  G11C13/00

    Abstract: A memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.

    Signal conversion based on complimentary analog signal pairs
    47.
    发明授权
    Signal conversion based on complimentary analog signal pairs 有权

    公开(公告)号：US10529394B2

    公开(公告)日：2020-01-07

    申请号：US16117509

    申请日：2018-08-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Ali Shafiee Ardestani ,  Naveen Muralimanohar ,  Brent Buchanan

    IPC: G11C7/16 ,  G11C7/22 ,  H03K21/02 ,  H03M1/34 ,  H03M1/66

    Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

    FINITE STATE MACHINES
    48.
    发明申请
    FINITE STATE MACHINES 审中-公开

    公开(公告)号：US20190235458A1

    公开(公告)日：2019-08-01

    申请号：US16354076

    申请日：2019-03-14

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng

    IPC: G05B19/045 ,  G11C15/04

    CPC classification number: G05B19/045 ,  G05B2219/23289 ,  G11C7/1006 ,  G11C15/04

    Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

    Resistive memory arrays for performing multiply-accumulate operations
    49.
    发明授权
    Resistive memory arrays for performing multiply-accumulate operations 有权

    公开(公告)号：US10339202B2

    公开(公告)日：2019-07-02

    申请号：US16213385

    申请日：2018-12-07

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Brent Buchanan

    IPC: G06F17/16 ,  G06F7/544 ,  G11C13/00 ,  G06F7/523 ,  G11C7/10 ,  G06F7/50

    Abstract: In one example in accordance with the present disclosure a resistive memory array is described. The array includes a number of resistive memory elements to receive a common-valued read signal. The array also includes a number of multiplication engines to perform a multiply operation by receiving a memory element output from a corresponding resistive memory element, receiving an input signal, and generating a multiplication output based on a received memory element output and a received input signal. The array also includes an accumulation engine to sum multiplication outputs from the number of multiplication engines.

    Multiply-Acumulate Circuits
    50.
    发明申请
    Multiply-Acumulate Circuits 审中-公开

    公开(公告)号：US20190114141A1

    公开(公告)日：2019-04-18

    申请号：US16218636

    申请日：2018-12-13

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

    IPC: G06F7/523 ,  G06F7/544

    Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.

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