公开(公告)号：US20070082446A1

公开(公告)日：2007-04-12

申请号：US11246908

申请日：2005-10-07

申请人： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

发明人： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/115 ,  H01L21/76897 ,  H01L27/11568

摘要： A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

摘要翻译： 提供了用于制造堆叠的非易失性存储单元的方法。 提供具有形成埋入位线的多个扩散区域的半导体晶片。 电荷捕获层和导电层沉积在半导体晶片的表面上。 在导电层的顶部使用掩模层，形成绝缘层的接触孔。 蚀刻停止层沉积在半导体晶片的表面上。 在蚀刻停止层上方，沉积介电层并图案化以形成接触孔。 随后，接触孔通过蚀刻停止层和绝缘层扩大到埋入位线。

公开(公告)号：US07159786B2

公开(公告)日：2007-01-09

申请号：US10925882

申请日：2004-08-23

申请人： Jurgen Fischer ,  Herbert Palm ,  Frank Puschner ,  Josef Willer

发明人： Jurgen Fischer ,  Herbert Palm ,  Frank Puschner ,  Josef Willer

IPC分类号： G06K19/06

CPC分类号： G06K19/07747 ,  G06K19/07743 ,  H01L2224/48091 ,  H01L2924/00014

摘要： Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body, external contact elements arranged on the carrier and electrically connected to the chip via conductor runs, and a cover covering the recess in operative connection with the carrier such that the carrier is held along the bottom in the recess, wherein the external contact elements and the chip are arranged on a same side of the carrier.

摘要翻译： 数据载体卡具有扁平形式的卡体，并且具有凹槽，载体，布置在载体上的芯片并插入卡体的凹部中，外部接触元件布置在载体上并电连接到芯片通孔导体 并且覆盖与载体可操作地连接的凹部的盖，使得载体沿着凹部中的底部保持，其中外部接触元件和芯片布置在载体的同一侧上。

公开(公告)号：US07094648B2

公开(公告)日：2006-08-22

申请号：US11023041

申请日：2004-12-27

申请人： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig ,  Josef Willer

发明人： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig ,  Josef Willer

IPC分类号： H01L21/8236

CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

摘要： In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

摘要翻译： 在该方法中，蚀刻沟槽，并且在其间，位线（8）分别布置在掺杂的源极/漏极区域（3,4）上。 存储层（5,6,7）被施加，栅电极（2）布置在沟槽壁处。 在向栅极电极（2）引入向多个沟槽中引入的多晶硅之后，以平坦化的方式将顶面进行研磨，直到到达覆盖层（16）的顶侧，然后将多晶硅层 （18），其被设置用于字线，并且被图案化以形成字线。

公开(公告)号：US07087500B2

公开(公告)日：2006-08-08

申请号：US10894348

申请日：2004-07-19

申请人： Frank Lau ,  Josef Willer

发明人： Frank Lau ,  Josef Willer

IPC分类号： H01L21/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

摘要翻译： 存储单元包括在半导体本体的顶侧的源极/漏极区之间的沟道区，并且相对于纵向方向横向地设置有形成在半导体材料中的凸起。 这导致径向电场的强度的均匀分布，并且避免了在通道区​​域的横向边缘处的场强尖峰。 存储层序列位于通道区域和栅电极之间，作为字线的一部分。

公开(公告)号：US07049651B2

公开(公告)日：2006-05-23

申请号：US10715142

申请日：2003-11-17

申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.

摘要翻译： 电荷捕获层包括在源极和漏极结上方的两个条带。 选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。 通过将热孔单独注入热孔进行两位存储来执行编程。

公开(公告)号：US07041545B2

公开(公告)日：2006-05-09

申请号：US10795611

申请日：2004-03-08

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573

摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

公开(公告)号：US20060038220A1

公开(公告)日：2006-02-23

申请号：US10921766

申请日：2004-08-19

申请人： Karl-Heinz Kusters ,  Josef Willer ,  Corvin Liaw

发明人： Karl-Heinz Kusters ,  Josef Willer ,  Corvin Liaw

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/792

摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

摘要翻译： 位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。 浮栅电极布置在所述上​​表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。 浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。

公开(公告)号：US20050242388A1

公开(公告)日：2005-11-03

申请号：US10835390

申请日：2004-04-30

申请人： Josef Willer ,  Frank Lau

发明人： Josef Willer ,  Frank Lau

IPC分类号： G11C16/02 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78645

摘要： The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

摘要翻译： 本发明涉及一种闪存单元，其包括具有包括沟道区和源 - 漏区的有源区的硅衬底，所述有源区包括突出部分，所述突出部分至少包括所述沟道区; 形成在所述有源区的表面上的隧道电介质层; 形成在用于存储电荷的所述隧道介电层的表面上的浮动栅极; 形成在所述浮置栅极的表面上的栅极间耦合电介质层和形成在所述栅极间耦合电介质层的表面上的控制栅极，其中所述浮动栅极形成为具有至少部分地具有沟槽形状 包围所述有源区域的所述突出部分。 本发明还涉及一种包括这种闪存单元的闪速存储器件及其制造方法。

公开(公告)号：US06960505B2

公开(公告)日：2005-11-01

申请号：US10706841

申请日：2003-11-12

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66833 ,  H01L29/7923 ,  Y10S438/954

摘要： A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge carriers, which are trapped over the source region and over the drain region, is prevented. The memory layer is limited to regions over the parts of the source region and of the drain region facing the channel and is embedded all around in oxide.

摘要翻译： 用于在源极区域和漏极区域上捕获电荷载流子的存储层在沟道上被中断，从而防止了俘获在源极区域和漏极区域上方的电荷载流子的扩散。 存储层被限制在源区域和漏极区域的面向通道的部分上的区域，并且被全部包埋在氧化物中。

公开(公告)号：US20050227426A1

公开(公告)日：2005-10-13

申请号：US10815223

申请日：2004-03-31

申请人： Joachim Deppe ,  Josef Willer

发明人： Joachim Deppe ,  Josef Willer

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material of shallow trench isolations running across the wordlines.

摘要翻译： 在包括电荷捕获存储器单元的存储单元阵列中，沿用于将相邻存储器单元的源极/漏极区域连接到位线的字线方向的局部互连通过在上部的半导体材料的侧壁上选择性沉积硅或多晶硅桥来形成 浅沟槽隔离物的电介质材料中的凹槽穿过字线。