公开(公告)号：US07499503B2

公开(公告)日：2009-03-03

申请号：US11728519

申请日：2007-03-26

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

IPC分类号： H04L27/36

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

公开(公告)号：US07415079B2

公开(公告)日：2008-08-19

申请号：US10865456

申请日：2004-06-10

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

IPC分类号： H03D1/00 ,  H03M13/03

CPC分类号： H03M13/3922 ,  H03M13/1102 ,  H03M13/258 ,  H03M13/275 ,  H03M13/2906 ,  H03M13/2939 ,  H03M13/2957 ,  H03M13/3927 ,  H03M13/4107 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0071

摘要： Decoder design adaptable to decode coded signals using min* or max* processing. A very efficient means of min* processing or max* processing may be performed within a communication device to assist in the very complex and cumbersome calculations that are employed when decoding coded signals. The types of coded signals that may be decoded using min* processing or max* processing are varied, and they include LDPC (Low Density Parity Check) coded signals, turbo coded signals, and TTCM (Turbo Trellis Coded Modulation) coded signals, among other coded signal types. Many of the calculations and/or determinations performed within min* processing or max* processing are performed simultaneously and in parallel of one another thereby ensuring very fast operation. In a finite precision digital implementation, when certain calculated bits of min* or max* processing are available, they govern selection of resultants from among multiple calculations and determinations made simultaneously and in parallel.

摘要翻译： 解码器设计适用于使用最小*或最大*处理解码编码信号。 可以在通信设备内执行min *处理或max *处理的非常有效的方法，以帮助解码编码信号时所采用的非常复杂且繁琐的计算。 可以使用min *处理或max *处理来解码的编码信号的类型是不同的，并且它们包括LDPC（低密度奇偶校验）编码信号，turbo编码信号和TTCM（Turbo网格编码调制）编码信号，以及其他 编码信号类型。 在min *处理或max *处理之内执行的许多计算和/或确定在彼此并行并行地执行，从而确保非常快速的操作。 在有限精度数字实现中，当某些计算的min *或max *处理的位可用时，它们可以对多个计算中的结果进行选择，同时并行地进行确定。

公开(公告)号：US07395487B2

公开(公告)日：2008-07-01

申请号：US11171568

申请日：2005-06-30

申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen

发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen

IPC分类号： H03M13/00 ,  H03M13/03 ,  G06F11/00 ,  H03D1/00

CPC分类号： H04L27/34 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/658 ,  H04L27/18

摘要： Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**− (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†− (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.

摘要翻译： 支持LDPC（低密度奇偶校验）解码器中的位节点和校验节点处理的公共电路。 提出了一种新颖的方法，其中解码器可以使用相同的电路来执行相对于位节点的边缘消息的更新，以及在解码LDPC编码信号的上下文中关于校验节点的边缘消息的更新。 此外，提出了几个非常有效的架构来执行涉及到关于校验节点的边缘消息的更新的校验节点处理。 一个实施例使用min **（min-double-star）处理结合min ** - （min-double-star-minus）处理来执行校验节点处理。 另一个实施例使用min††（最小双匕首）处理结合最小† - （最小匕首 - 减号）处理来执行校验节点处理。 此外，可以实现单个FIFO以在并行解码实现中服务多个宏块。

公开(公告)号：US07383493B2

公开(公告)日：2008-06-03

申请号：US10802011

申请日：2004-03-16

申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H04L1/005 ,  G11B20/1833 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/25 ,  H03M13/255 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/4161 ,  H03M13/45 ,  H03M13/6583 ,  H04L1/0041 ,  H04L1/0058 ,  H04L1/006 ,  H04L1/0071 ,  H04L1/1671 ,  H04L27/18 ,  H04L27/2602

摘要： LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until sufficient degree of precision is achieved. The symbol node updating of the bit edge messages uses symbol metrics corresponding to the symbol being decoded and the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages uses the bit edge messages most recently updated by symbol node updating. The symbol node updating computes possible soft symbol estimates. LDPC coded modulation hybrid decoding can decode an LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) signal having a symbol mapped using non-Gray code mapping. By using the non-Gray code mapping, a performance improvement is achieved over an only Gray code mapping system.

摘要翻译： 使用非格雷码的LDPC（低密度奇偶校验）编码调制混合解码，以提高性能。 对于预定数量的解码迭代，或者直到达到足够的精度，连续替代地对位边消息执行检查节点更新和符号节点更新。 比特边消息的符号节点更新使用与正被解码的符号相对应的符号度量和最近由校验节点更新更新的位边消息。 位边消息的校验节点更新使用最近由符号节点更新更新的位边消息。 符号节点更新计算可能的软符号估计。 LDPC编码调制混合解码可以解码具有使用非格雷码映射的符号映射的LDPC-BICM（低密度奇偶校验位交错编码调制）信号。 通过使用非格雷码映射，仅通过格雷码映射系统实现性能提升。

公开(公告)号：US07383485B2

公开(公告)日：2008-06-03

申请号：US11172329

申请日：2005-06-30

申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen

发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen

IPC分类号： H03M13/45

CPC分类号： H03M13/112 ,  H03M13/1105 ,  H03M13/1117 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/6583 ,  H04L1/0003 ,  H04L1/0057

摘要： Fast min*− (min-star-minus) or max*− (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*− and/or min*− processing allows for very fast operation when compared to prior art approaches.

摘要翻译： LDPC（低密度奇偶校验）解码器中的快速min * - （min-star-minus）或max * - （max-star-minus）电路。 提出了一种新颖有效的方法，通过该方法可以在各种类型的解码器中执行校验节点处理所需的某些计算。 这里呈现的功能和体系结构可应用于LDPC解码器，并且还可以用于可操作以解码其他类型的编码信​​号的其他类型的解码器。 与现有技术方法相比，最大*和/或最小*处理的总体结果的某些部分的并行和有时同时的计算和确定允许非常快速的操作。

公开(公告)号：US07370265B2

公开(公告)日：2008-05-06

申请号：US11701155

申请日：2007-02-01

申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

IPC分类号： H03M13/03

CPC分类号： H04L1/005 ,  H03M5/20 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1148 ,  H03M13/1177 ,  H03M13/255 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/4161 ,  H03M13/45 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/0058 ,  H04L1/006 ,  H04L1/0071 ,  H04L27/18 ,  H04L27/183 ,  H04L27/186 ,  H04L27/2053

摘要： Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords (e.g., an MLC block) are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks that corporately form an MLC block. Encoded bits from levels of the MLC block are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.

摘要翻译： 基于具有多个映射的MLC（多级代码）信号的带宽高效编码调制方案。 多个地图的使用适用于各种类型的编码信​​号，包括多级LDPC编码调制信号和其他MLC信号，以便在试图达到香农限制的持续努力中提供显着的性能增益。 在LDPC编码信号的情况下，从各自对应的LDPC编码器生成各种级别的LDPC码字（例如，MLC块）。 这些各种级别的LDPC码字被排列成合并形成MLC块的多个子块。 MLC块的编码比特被排列成根据至少两个调制映射的符号。 每个调制包括星座形状和相应的映射。 与仅使用单个映射的编码器相比，使用多个映射提供了改进的性能。

公开(公告)号：US07321633B1

公开(公告)日：2008-01-22

申请号：US10338432

申请日：2003-01-08

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

IPC分类号： H04L23/02

CPC分类号： H04L27/0008 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0068 ,  H04L2001/0098

摘要： Determination of variable code rates for a rate control sequence. A rate control sequence governs symbols that are to be encoded and/or decoded. A different rate control value may be used to control code rates of individual symbols in a signal. The determination of the variable code rates may be performed based on a number of parameters including a communication system's operating conditions and/or the signal to noise ratio (SNR) of a communication channel. The variable code rates may also adaptively change, in real time (if desired), in response to the communication system's operating conditions including a communication channel's SNR. The variable code rate functionality may also be adaptively tailored to match the SNR of a communication receiver's communication channel within a multi-receiver communication system; those receivers in a beam spot (higher SNR) may operate using a higher code rate than those receivers further away from the spot (lower SNR).

摘要翻译： 确定速率控制序列的可变代码率。 速率控制序列控制要被编码和/或解码的符号。 可以使用不同的速率控制值来控制信号中的各个符号的码率。 可以基于包括通信系统的操作条件和/或通信信道的信噪比（SNR）的参数的数量来执行可变码率的确定。 响应于包括通信信道的SNR的通信系统的操作条件，可变码率也可以实时（如果需要）自适应地改变。 也可以自适应地定制可变码率功能以匹配多接收机通信系统内的通信接收机的通信信道的SNR; 波束点（较高SNR）中的那些接收机可以使用比远离该点（较低SNR）的那些接收机更高的码率来操作。

公开(公告)号：US07197690B2

公开(公告)日：2007-03-27

申请号：US11017087

申请日：2004-12-20

申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

IPC分类号： H03M13/03

CPC分类号： H04L1/005 ,  H03M5/20 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1148 ,  H03M13/1177 ,  H03M13/255 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/4161 ,  H03M13/45 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/0058 ,  H04L1/006 ,  H04L1/0071 ,  H04L27/18 ,  H04L27/183 ,  H04L27/186 ,  H04L27/2053

摘要： Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks. Encoded bits from multiple level LDPC codewords within each of the sub-blocks are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.

摘要翻译： 基于具有多个映射的MLC（多级代码）信号的带宽高效编码调制方案。 多个地图的使用适用于各种类型的编码信​​号，包括多级LDPC编码调制信号和其他MLC信号，以便在试图达到香农限制的持续努力中提供显着的性能增益。 在LDPC编码信号的情况下，从各自对应的LDPC编码器生成各种级别的LDPC码字。 这些各种级别的LDPC码字被排列成多个子块。 每个子块内的多级LDPC码字的编码比特被排列成根据至少两个调制映射的符号。 每个调制包括星座形状和相应的映射。 这种使用多个映射

公开(公告)号：US07107511B2

公开(公告)日：2006-09-12

申请号：US10369168

申请日：2003-02-19

申请人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

发明人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

IPC分类号： H03M13/00

CPC分类号： H04L1/005 ,  H04L1/0057

摘要： Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

摘要翻译： 使用min *，min **，max *或max **的低密度奇偶校验（LDPC）码解码器及其各自的反转。 首次演示了用于解码LDPC编码信号的min *处理。 另外，当执行执行使用LDPC码编码的信号的解码所需的计算时，也可以采用max *，min **或max **（及其各自的反转）。 当解码涉及从多个可能值中确定最小和/或最大值或最小和/或最大对数校正值时，可以采用这些新参数来为LDPC码提供大大改进的解码处理。 采用本文所述的最小*，最大*，最小**或最大**（及其相应的反转）解码处理，在LDPC编码信号的解码中采用的处理步骤的总数显着减少。

公开(公告)号：US07065695B2

公开(公告)日：2006-06-20

申请号：US10264647

申请日：2002-10-04

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Linda K. Lau

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Linda K. Lau

IPC分类号： H03M13/00

CPC分类号： H04L1/005 ,  H03M13/256 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2785 ,  H03M13/2957 ,  H03M13/4123 ,  H03M13/4161 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Metric calculation design for variable code rate decoding of broadband trellis, TCM (trellis coded modulated), or TTCM (turbo trellis coded modulation). A single design can accommodate a large number of code rates by multiplexing the appropriate paths within the design. By controlling where to scale for any noise of a received symbol within a received signal, this adaptable design may be implemented in a manner that is very efficient in terms of performance, processing requirements (such as multipliers and gates), as well as real estate consumption. In supporting multiple code rates, appropriately selection of the coefficients of the various constellations employed, using the inherent redundancy and symmetry along the I and Q axes, can result in great savings of gates borrowing upon the inherent redundancy contained therein; in addition, no subtraction (but only summing) need be performed when capitalizing on this symmetry.

摘要翻译： 宽带网格，TCM（网格编码调制）或TTCM（turbo网格编码调制）的可变码率解码的度量计算设计。 单一设计可以通过在设计中复用适当的路径来适应大量的代码率。 通过控制在接收信号中对接收到的符号的任何噪声进行缩放的位置，可以以在性能，处理要求（例如乘法器和门）等方面非常有效的方式来实现这种适应性设计，以及房地产 消费。 在支持多个码率的情况下，使用沿I和Q轴的固有冗余和对称性适当地选择所使用的各种星座的系数，可以大大节省借助于其中包含的固有冗余的门; 此外，当利用这种对称性时，不需要执行减法（但只有求和）。