公开(公告)号：US08735296B2

公开(公告)日：2014-05-27

申请号：US13552035

申请日：2012-07-18

申请人： Ryan O. Jung ,  Sivananda K. Kanakasabapathy

发明人： Ryan O. Jung ,  Sivananda K. Kanakasabapathy

IPC分类号： H01L21/311

CPC分类号： H01L21/28132 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823456 ,  H01L29/66575 ,  H01L29/78

摘要： A method of forming multiple different width dimension features simultaneously. The method includes forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer.

摘要翻译： 同时形成多个不同宽度尺寸特征的方法。 该方法包括形成由不同心轴上的适形层的不同组合形成的不同宽度的多个侧壁间隔物，去除心轴，以及同时将不同侧壁间隔物的图案转移到下面的层中。

公开(公告)号：US08637930B2

公开(公告)日：2014-01-28

申请号：US13272409

申请日：2011-10-13

申请人： Takashi Ando ,  Josephine B. Chang ,  Sivananda K. Kanakasabapathy ,  Pranita Kulkarni ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Takashi Ando ,  Josephine B. Chang ,  Sivananda K. Kanakasabapathy ,  Pranita Kulkarni ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66803 ,  H01L29/785

摘要： A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.

摘要翻译： 晶体管，例如FinFET，包括设置在衬底上的栅极结构。 栅极结构具有宽度以及限定栅极结构的两个相对侧壁的长度和高度。 晶体管还包括通过栅极结构的侧壁的源极区域和漏极区域之间的至少一个导电沟道; 设置在所述栅极结构上方的电介质层和在所述栅极结构外部的所述导电沟道的部分; 以及介电层下面的气隙。 气隙设置成与栅极结构的侧壁相邻，并且用于减小晶体管的寄生电容。 还公开了制造晶体管的至少一种方法。

公开(公告)号：US08637384B2

公开(公告)日：2014-01-28

申请号：US13617426

申请日：2012-09-14

申请人： Takashi Ando ,  Josephine B. Chang ,  Sivananda K. Kanakasabapathy ,  Pranita Kulkarni ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Takashi Ando ,  Josephine B. Chang ,  Sivananda K. Kanakasabapathy ,  Pranita Kulkarni ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/336 ,  H01L21/283

CPC分类号： H01L29/66803 ,  H01L29/785

摘要： Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.

摘要翻译： 公开了通过在源极区域和漏极区域之间在衬底上形成至少一个导电沟道来制造晶体管，例如FinFET的方法; 形成栅极结构以设置在所述沟道的一部分上，所述栅极结构具有限定所述栅极结构的两个相对侧壁的宽度和长度以及高度，并且形成为使得所述沟道穿过所述侧壁; 在侧壁上形成间隔物; 在所述通道上形成外延硅层; 去除垫片; 以及形成电介质层，以设置在所述栅极结构和所述沟道结构的外部的部分上，使得电容减小气隙位于所述电介质层的下面，并且在所述栅极结构的侧壁附近设置在区域 以前被隔离物占据。

公开(公告)号：US08455364B2

公开(公告)日：2013-06-04

申请号：US12613682

申请日：2009-11-06

申请人： Sivananda K. Kanakasabapathy

发明人： Sivananda K. Kanakasabapathy

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795

摘要： In one non-limiting exemplary embodiment, a method includes: providing a structure having at least one lithographic layer on a substrate, where the at least one lithographic layer includes a planarization layer (PL); forming a sacrificial mandrel by patterning at least a portion of the at least one lithographic layer using a photolithographic process, where the sacrificial mandrel includes at least a portion of the PL; and producing at least one microstructure by using the sacrificial mandrel in a sidewall image transfer process.

摘要翻译： 在一个非限制性示例性实施例中，一种方法包括：提供在衬底上具有至少一个光刻层的结构，其中所述至少一个光刻层包括平坦化层（PL）; 通过使用光刻工艺图案化所述至少一个光刻层的至少一部分来形成牺牲心轴，其中所述牺牲心轴包括所述PL的至少一部分; 以及通过在侧壁图像转印过程中使用牺牲心轴来生产至少一个微结构。

公开(公告)号：US20120181613A1

公开(公告)日：2012-07-19

申请号：US13009271

申请日：2011-01-19

申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Sivananda K. Kanakasabapathy

发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Sivananda K. Kanakasabapathy

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/66477 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/78

摘要： A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer.

摘要翻译： 一种用于形成场效应晶体管器件的方法包括在衬底上形成第一栅极堆叠和第二栅极叠层，在第二栅极堆叠上沉积第一光致抗蚀剂材料和衬底的一部分，将衬底的暴露区域中的离子注入到 限定与第一栅极堆叠相邻的第一源极区域和第一漏极区域，在第一源极区域，第一栅极堆叠层，第一漏极区域和第一光致抗蚀剂材料上沉积第一保护层，去除第一保护层 以露出第一光致抗蚀剂材料并且限定设置在第一源极区域和第一漏极区域的一部分上的第一间隔物，去除第一光致抗蚀剂材料，以及移除第一间隔物。

公开(公告)号：US20120068346A1

公开(公告)日：2012-03-22

申请号：US12885665

申请日：2010-09-20

申请人： SHOM PONOTH ,  David V. Horak ,  Elbert E. Huang ,  Sivananda K. Kanakasabapathy ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： SHOM PONOTH ,  David V. Horak ,  Elbert E. Huang ,  Sivananda K. Kanakasabapathy ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L23/53266 ,  H01L21/32139 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

摘要翻译： 为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。 在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。 通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

公开(公告)号：US20110111596A1

公开(公告)日：2011-05-12

申请号：US12613682

申请日：2009-11-06

申请人： Sivananda K. Kanakasabapathy

发明人： Sivananda K. Kanakasabapathy

IPC分类号： H01L21/30

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795

摘要： In one non-limiting exemplary embodiment, a method includes: providing a structure having at least one lithographic layer on a substrate, where the at least one lithographic layer includes a planarization layer (PL); forming a sacrificial mandrel by patterning at least a portion of the at least one lithographic layer using a photolithographic process, where the sacrificial mandrel includes at least a portion of the PL; and producing at least one microstructure by using the sacrificial mandrel in a sidewall image transfer process.

摘要翻译： 在一个非限制性示例性实施例中，一种方法包括：提供在衬底上具有至少一个光刻层的结构，其中所述至少一个光刻层包括平坦化层（PL）; 通过使用光刻工艺图案化所述至少一个光刻层的至少一部分来形成牺牲心轴，其中所述牺牲心轴包括所述PL的至少一部分; 以及通过在侧壁图像转印过程中使用牺牲心轴来生产至少一个微结构。

公开(公告)号：US07782660B2

公开(公告)日：2010-08-24

申请号：US12052326

申请日：2008-03-20

申请人： Solomon Assefa ,  Sivananda K. Kanakasabapathy ,  Janusz Jozef Nowak ,  Philip L Trouilloud

发明人： Solomon Assefa ,  Sivananda K. Kanakasabapathy ,  Janusz Jozef Nowak ,  Philip L Trouilloud

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  G11C11/1659 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for shielding magnetic memory cells from magnetic fields are presented. In accordance with aspects of the invention, a magnetic storage element is formed with at least one conductive segment electrically coupled to the magnetic storage element. At least a portion of the conductive segment is surrounded with a magnetic liner. The magnetic liner is operative to divert at least a portion of a magnetic field created by a current passing through the conductive segment away from the magnetic storage element.

摘要翻译： 介绍了磁场对磁记忆体进行屏蔽的技术。 根据本发明的方面，磁存储元件形成有至少一个电耦合到磁存储元件的导电段。 导电段的至少一部分被磁性衬垫包围。 磁性衬垫可操作以将由导电段流过的电流产生的磁场的至少一部分转移离开磁存储元件。

公开(公告)号：US07642147B1

公开(公告)日：2010-01-05

申请号：US12242977

申请日：2008-10-01

申请人： Sivananda K. Kanakasabapathy

发明人： Sivananda K. Kanakasabapathy

IPC分类号： H01L21/8238

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

摘要： A method for removing sidewall spacers. The method includes: (a) forming a gate stack on a substrate; after (a), (b) forming dielectric spacers on sidewalls of the gate stack; after (b), (c) forming a dielectric sacrificial layer over the substrate and on the gate stack where the substrate and the gate stack are not covered by the spacers; and after (c), (d) removing the sacrificial layer and the spacers in a etch process by etching the sacrificial layer until the spacers are exposed and thereafter simultaneously etching the sacrificial layer and the spacers until the sacrificial layer and the spacers are removed. Methods for spacer removal from PFETs when a stress layer is formed over the NFETs are also disclosed.

摘要翻译： 一种去除侧壁间隔物的方法。 该方法包括：（a）在基板上形成栅叠层; （a）之后，（b）在栅叠层的侧壁上形成电介质间隔物; （b）之后，（c）在基板和栅叠层上形成绝缘牺牲层，其中衬底和栅极堆叠不被间隔物覆盖; 在（c）之后，（d）通过蚀刻牺牲层去除牺牲层和间隔物，直到间隔物被暴露，然后同时蚀刻牺牲层和间隔物，直到除去牺牲层和间隔物。 还公开了当在NFET上形成应力层时从PFET去除间隔物的方法。

公开(公告)号：US07507633B2

公开(公告)日：2009-03-24

申请号：US11369516

申请日：2006-03-07

申请人： Sivananda K. Kanakasabapathy ,  David W. Abraham

发明人： Sivananda K. Kanakasabapathy ,  David W. Abraham

IPC分类号： H01L21/76

CPC分类号： H01L23/544 ,  H01L27/222 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.

摘要翻译： 用于实现半导体器件结构的对准的方法包括在该结构的较低级别内形成第一组和第二组对准标记，第二组对准标记与第一组对准标记相邻。 在较低层上形成不透明层，包括第一组和第二组对准标记。 对应于所述第一组对准标记的位置的不透明层的一部分被打开，以使第一组光学可见，而第二组对准标记最初保持被不透明层覆盖。 使用光学可见的第一组对准标记图案化不透明层，其中在第一组在不透明层的图案化期间第一组变得损坏的情况下，第二组对准标记保持可用于随后的对准操作。