公开(公告)号：US20110147755A1

公开(公告)日：2011-06-23

申请号：US12972994

申请日：2010-12-20

申请人： Hidekazu MIYAIRI ,  Shinya SASAGAWA ,  Motomu KURATA

发明人： Hidekazu MIYAIRI ,  Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L29/786

CPC分类号： H01L29/78678 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78648

摘要： A thin film transistor having favorable electric characteristics with high productively is provided. The thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, an impurity semiconductor layer which is in contact with part of the semiconductor layer and functions as a source region and a drain region, and a wiring in contact with the impurity semiconductor layer. The semiconductor layer includes a microcrystalline semiconductor region having a concave-convex shape, which is formed on the gate insulating layer side, and an amorphous semiconductor region in contact with the microcrystalline semiconductor region. A barrier region is provided between the semiconductor layer and the wiring.

摘要翻译： 提供了具有良好的电特性的高效生产的薄膜晶体管。 薄膜晶体管包括覆盖栅极的栅极绝缘层，与栅极绝缘层接触的半导体层，与半导体层的一部分接触并用作源极区域和漏极区域的杂质半导体层， 以及与杂质半导体层接触的布线。 半导体层包括形成在栅绝缘层侧的具有凹凸形状的微晶半导体区域和与微晶半导体区域接触的非晶半导体区域。 在半导体层和布线之间设置有阻挡区域。

公开(公告)号：US20100019337A1

公开(公告)日：2010-01-28

申请号：US12575910

申请日：2009-10-08

申请人： Shinya SASAGAWA ,  Shinya Hasegawa ,  Hidekazu Takahashi ,  Tatsuya Arao

发明人： Shinya SASAGAWA ,  Shinya Hasegawa ,  Hidekazu Takahashi ,  Tatsuya Arao

IPC分类号： H01L31/0232 ,  H01L31/0352

CPC分类号： H01L31/035281 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/14643 ,  Y02E10/50

摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.

公开(公告)号：US20070278606A1

公开(公告)日：2007-12-06

申请号：US11737477

申请日：2007-04-19

申请人： Shinya SASAGAWA ,  Shinya HASEGAWA ,  Hidekazu TAKAHASHI ,  Tatsuya ARAO

发明人： Shinya SASAGAWA ,  Shinya HASEGAWA ,  Hidekazu TAKAHASHI ,  Tatsuya ARAO

IPC分类号： H01L31/075 ,  H01L31/18

CPC分类号： H01L31/035281 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/14643 ,  Y02E10/50

摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.

摘要翻译： 本发明的目的是提供一种具有不同锥角的侧面的光电转换元件，该光电转换元件逐步进行光电转换层的蚀刻。 与pn光电二极管相比，pin光电二极管具有高响应速度，但是具有大的暗电流的缺点。 认为暗电流的一个原因是通过在蚀刻中产生并沉积在光电转换层的侧表面上的蚀刻残余物导电。 光电转换元件的泄漏电流通过形成侧表面具有两个不同的锥形形状的结构而降低，通常具有均匀的表面，使得光电转换层具有p层的侧表面和侧表面 的n层，它们不在同一平面。

公开(公告)号：US20100176461A1

公开(公告)日：2010-07-15

申请号：US12731824

申请日：2010-03-25

申请人： Shinya SASAGAWA

发明人： Shinya SASAGAWA

IPC分类号： H01L29/49

CPC分类号： H01L21/76804 ,  H01L23/485 ,  H01L27/124 ,  H01L29/41733 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed. A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.

摘要翻译： 提出一种容易制造半导体器件的方法，其中防止了源电极或漏电极的厚度变化或断开。 半导体器件包括形成在绝缘基板上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 至少形成在所述第一绝缘层和所述第二绝缘层中的至少形成在所述半导体层上的开口部; 以及形成在所述开口中的所述第二绝缘层的侧表面处的台阶部。

公开(公告)号：US20080237876A1

公开(公告)日：2008-10-02

申请号：US12046881

申请日：2008-03-12

申请人： Shinya SASAGAWA

发明人： Shinya SASAGAWA

IPC分类号： H01L23/52 ,  H01L21/28

CPC分类号： H01L21/76804 ,  H01L23/485 ,  H01L27/124 ,  H01L29/41733 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.

摘要翻译： 提出一种容易制造其中防止源电极或漏电极的厚度变化或断开的半导体器件的方法。一种半导体器件包括形成在绝缘基板上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 至少形成在所述第一绝缘层和所述第二绝缘层中的至少形成在所述半导体层上的开口部; 以及形成在所述开口中的所述第二绝缘层的侧表面处的台阶部。

公开(公告)号：US20120288993A1

公开(公告)日：2012-11-15

申请号：US13466664

申请日：2012-05-08

申请人： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Hiroshi FUJIKI

发明人： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Hiroshi FUJIKI

IPC分类号： H01L21/34

CPC分类号： H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

摘要： To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

摘要翻译： 为了建立包括In-Sn-Zn-O类半导体的半导体器件的制造中的加工技术。 通过使用含氯气体如Cl 2，BCl 3，SiCl 4等的干蚀刻来选择性地蚀刻In-Sn-Zn-O系半导体层。 在形成源极电极层和漏电极层时，可以选择性地蚀刻与In-Sn-Zn-O系半导体层接触的导电层，同时很少去除In-Sn-Zn-O系半导体层， 除了含有氯的气体之外，还使用含有氧或氟的气体。

公开(公告)号：US20110207269A1

公开(公告)日：2011-08-25

申请号：US13026520

申请日：2011-02-14

申请人： Shinya SASAGAWA ,  Masashi TSUBUKU ,  Hitoshi NAKAYAMA ,  Daigo SHIMADA

发明人： Shinya SASAGAWA ,  Masashi TSUBUKU ,  Hitoshi NAKAYAMA ,  Daigo SHIMADA

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66969 ,  H01L29/7869

摘要： A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

摘要翻译： 晶体管通过以下方法制造：包括：形成第一布线层; 形成第一绝缘膜以覆盖所述第一布线层; 在所述第一绝缘膜上形成半导体层; 在半导体层上形成导电膜; 并且对所述导电膜进行蚀刻的至少两个步骤以形成彼此分离的第二布线层，其中所述两个蚀刻步骤至少包括在导电膜的蚀刻速率为 高于半导体层的蚀刻速率，以及在导电膜和半导体层的蚀刻速率高于第一蚀刻工艺的蚀刻速率的条件下进行的第二蚀刻工艺。

公开(公告)号：US20090206494A1

公开(公告)日：2009-08-20

申请号：US12431170

申请日：2009-04-28

申请人： Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shigeharu MONOE

发明人： Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shigeharu MONOE

IPC分类号： H01L23/52 ,  C23F1/00 ,  H01L21/3205 ,  H05K1/00

CPC分类号： H01L27/3276 ,  G02F2001/13629 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L51/0021 ,  H01L51/0023 ,  H01L51/5281 ,  H01L2924/0002 ,  H05K3/06 ,  H05K2203/0315 ,  H05K2203/0346 ,  H05K2203/095 ,  H05K2203/1476 ,  H01L2924/00

摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.

摘要翻译： 公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。 还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。 此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。 根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于 第一个条件。

公开(公告)号：US20090111248A1

公开(公告)日：2009-04-30

申请号：US12247487

申请日：2008-10-08

申请人： Hideto OHNUMA ,  Tetsuya KAKEHATA ,  Akihisa SHIMOMURA ,  Shinya SASAGAWA ,  Motomu KURATA

发明人： Hideto OHNUMA ,  Tetsuya KAKEHATA ,  Akihisa SHIMOMURA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L21/02

CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/02686 ,  H01L21/268 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/84

摘要： A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the single crystal semiconductor layer.

摘要翻译： 通过源气体的激发产生等离子体并通过从单晶半导体衬底的表面之一添加包含在等离子体中的离子种类而形成损伤区域; 在单晶半导体衬底的另一个表面上形成绝缘层; 支撑衬底牢固地附接到单晶半导体衬底，以便在其间插入绝缘层的单晶半导体衬底; 通过加热单晶半导体衬底，在损伤区域处分离成与单晶半导体层相连的支撑衬底和部分单晶半导体衬底; 在附着于支撑基板的单晶半导体层的表面进行干蚀刻， 通过用激光束照射单晶半导体层来使单晶半导体层重结晶，从而熔化至少一部分单晶半导体层。

公开(公告)号：US20120289005A1

公开(公告)日：2012-11-15

申请号：US13466480

申请日：2012-05-08

申请人： Tetsuhiro TANAKA ,  Shinya SASAGAWA

发明人： Tetsuhiro TANAKA ,  Shinya SASAGAWA

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/78696 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78648 ,  H01L29/78672 ,  H01L29/788

摘要： A thin film transistor having low off-state current and excellent electrical characteristics can be manufactured. In an inverted staggered thin film transistor including a semiconductor film in which at least a microcrystalline semiconductor region and an amorphous semiconductor region are stacked, a conductive film and an etching protective film are stacked over the semiconductor film; a mask is formed over the etching protective film; first etching treatment in which the etching protective film, the conductive film, and the amorphous semiconductor region are partly etched is performed; then, the mask is removed. Next, second etching treatment in which the exposed amorphous semiconductor region and the microcrystalline semiconductor region are partly dry-etched is performed using the etched etching protective film as a mask so that the microcrystalline semiconductor region is partly exposed to form a back channel region.

摘要翻译： 可以制造具有低截止电流和优异电特性的薄膜晶体管。 在包括半导体膜的倒置交错薄膜晶体管中，其中层叠有至少一个微晶半导体区域和非晶半导体区域，在半导体膜上层叠导电膜和蚀刻保护膜; 在蚀刻保护膜上形成掩模; 执行其中蚀刻保护膜，导电膜和非晶半导体区域被部分蚀刻的第一蚀刻处理; 然后，去除面具。 接下来，使用蚀刻蚀刻保护膜作为掩模进行其中暴露的非晶半导体区域和微晶半导体区域被部分干法蚀刻的第二蚀刻处理，使得微晶半导体区域部分地暴露以形成背沟道区域。