公开(公告)号：US08536017B2

公开(公告)日：2013-09-17

申请号：US13363312

申请日：2012-01-31

申请人： Masaru Kadoshima ,  Hiroshi Umeda ,  Tatsunori Kaneoka ,  Katsuyuki Horita

发明人： Masaru Kadoshima ,  Hiroshi Umeda ,  Tatsunori Kaneoka ,  Katsuyuki Horita

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.

摘要翻译： 在半导体衬底的主表面上形成聚硅氮烷膜，使得埋在宽度为0.2μm或更小的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平， 埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。 然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。

公开(公告)号：US20070241373A1

公开(公告)日：2007-10-18

申请号：US11577878

申请日：2005-10-18

申请人： Takashi Kuroi ,  Katsuyuki Horita ,  Masashi Kitazawa ,  Masato Ishibashi

发明人： Takashi Kuroi ,  Katsuyuki Horita ,  Masashi Kitazawa ,  Masato Ishibashi

IPC分类号： H01L29/768 ,  H01L21/76 ,  H01L29/00

CPC分类号： H01L21/823475 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/763 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.

摘要翻译： 在制造半导体器件的过程中，在衬底上形成第一层，并且蚀刻第一层和衬底以形成沟槽。 沟槽的内壁被热氧化。 在包括沟槽内部的衬底上沉积厚度等于或大于沟槽宽度的一半的第一导电膜。 通过化学机械抛光去除第一层上的第一导电膜，使得第一导电膜仅保留在沟槽中。 通过各向异性蚀刻第一导电膜，将沟槽中的第一导电膜的高度调节为低于衬底的表面。 通过化学气相沉积在衬底上沉积绝缘膜以覆盖沟槽中的第一导电膜的上表面。 绝缘膜通过化学机械抛光而变平，第一层被去除。

公开(公告)号：US20060270121A1

公开(公告)日：2006-11-30

申请号：US11381657

申请日：2006-05-04

申请人： Takashi Ipposhi ,  Katsuyuki Horita ,  Shigeto Maegawa

发明人： Takashi Ipposhi ,  Katsuyuki Horita ,  Shigeto Maegawa

IPC分类号： H01L21/84

CPC分类号： H01L21/76283

摘要： Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant. Then, after removing the resist and depositing an isolation oxide film on the whole surface, an isolation oxide film is flattened in good thickness precision in the height specified by the thickness of a silicon nitride film by performing CMP treatment which used the silicon nitride film as the polishing stopper.

摘要翻译： 即使制造使用部分和全部隔离组合使用技术进行元件隔离的绝缘隔离结构，也可以制造半导体器件的制造方法，该半导体器件可以制造半导体器件，其特征在于SOI层中形成绝缘隔离 获得了。 通过使用图案化的抗蚀剂和沟槽掩模作为掩模来进行内壁氧化膜和SOI层的蚀刻，形成穿透SOI层并到达嵌入绝缘层的完全隔离用沟槽。 此时，由于去除了在上部没有形成抗蚀剂的CVD氧化膜的一部分，由于氮化硅膜被CVD氧化膜保护，所以氮化硅膜的厚度保持恒定。 然后，在除去抗蚀剂并在整个表面上沉积隔离氧化物膜之后，通过进行使用氮化硅膜的CMP处理将隔离氧化物膜以由氮化硅膜的厚度规定的高度精确地平坦化，使用氮化硅膜作为 抛光止动器。

公开(公告)号：US06890837B2

公开(公告)日：2005-05-10

申请号：US10683359

申请日：2003-10-14

申请人： Takashi Kuroi ,  Katsuyuki Horita ,  Katsuomi Shiozawa

发明人： Takashi Kuroi ,  Katsuyuki Horita ,  Katsuomi Shiozawa

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/544 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L21/46

CPC分类号： H01L21/762 ,  H01L21/823481 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.

摘要翻译： 衬底表面（10S）被热氧化以形成氧化物膜。 图案化氧化膜，使得有源区域中的衬底表面（10S）暴露。 由此提供氧化膜（20）。 暴露的衬底表面（10S）被热氧化，以形成热氧化膜。 此后，至少在元件形成区域中除去该热氧化膜。 在暴露的基板表面（10S）上外延生长硅膜（41）。 此后，通过CMP对硅膜（41）进行抛光，使抛光后的硅膜的上表面的高度不超过氧化膜（20）的上表面。 接着，将硅膜的表面热氧化，形成热氧化膜。 在各种类型的离子注入之后，去除该热氧化膜。

公开(公告)号：US06548871B1

公开(公告)日：2003-04-15

申请号：US09543349

申请日：2000-04-05

申请人： Katsuyuki Horita ,  Takashi Kuroi ,  Yasuyoshi Itoh ,  Katsuomi Shiozawa

发明人： Katsuyuki Horita ,  Takashi Kuroi ,  Yasuyoshi Itoh ,  Katsuomi Shiozawa

IPC分类号： H01L2976

CPC分类号： H01L21/76895 ,  H01L21/76802 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/535 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.

摘要翻译： 属于彼此相邻的分离元件的两个源极/漏极区域（20）通过与形成栅电极的一部分的金属层（10）的高度相同的高度的金属层（14）连接。 在制造过程中，绝缘层（8）由除两个绝缘层（7）和（16）之外的其它材料制成。 两个绝缘层（7）和（16）作为用于将金属层（10），（14）和（15）埋入其中并由相同材料制成的模具。 因此，金属层（14）可以形成在与金属层（10）的高度相同的高度。 因此，通过布置在较短距离处的布线而连接的部分被连接，同时降低布线能力。

公开(公告)号：US06482718B2

公开(公告)日：2002-11-19

申请号：US09963432

申请日：2001-09-27

申请人： Katsuomi Shiozawa ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Katsuomi Shiozawa ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76235

摘要： A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure. Implantation of ions (15) in a polycrystalline silicon layer (3) from above through a silicon nitride film (2) produces an ion-implanted polycrystalline silicon layer (16). Since the ions (15) are an ionic species of element which acts to enhance oxidation, the implantation of the ions (15) changes the polycrystalline silicon layer (3) into the ion-implanted polycrystalline silicon layer (16) having a higher oxidation rate. In subsequent formation of a thermal oxide film (21) on the inner wall of a trench (5), exposed part of the ion-implanted polycrystalline silicon layer (16) is also oxidized, forming relatively wide polycrystalline silicon oxide areas (21a).

摘要翻译： 提供一种制造半导体器件的方法，即使器件尺寸减小，也可以防止沟槽隔离结构中的元件隔离区彼此隔离的半导体元件的工作特性的劣化。 通过氮化硅膜（2）将离子（15）从上方注入到多晶硅层（3）中产生离子注入的多晶硅层（16）。 由于离子（15）是用于增强氧化的元素的离子种类，离子（15）的注入将多晶硅层（3）改变为具有较高氧化速率的离子注入的多晶硅层（16） 。 在随后在沟槽（5）的内壁上形成热氧化膜（21）时，离子注入的多晶硅层（16）的暴露部分也被氧化，形成相当宽的多晶硅氧化物区域（21a）。

公开(公告)号：US06323102B1

公开(公告)日：2001-11-27

申请号：US09090422

申请日：1998-06-04

申请人： Katsuyuki Horita ,  Takashi Kuroi ,  Maiko Sakai

发明人： Katsuyuki Horita ,  Takashi Kuroi ,  Maiko Sakai

IPC分类号： H01L2176

CPC分类号： H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L21/76232

摘要： A method of manufacturing a semiconductor device having a microminiture trench isolation in which an insulating film is embedded by an HDP-CVD method comprising: a step of pre-planarization by conducting a dry etching selectively with respect to the insulating film laminated excessively on the surface of substrate, which is to be an active region, and a step of polishing by a CMP method in order to improve a surface planarity of the insulating film, wherein an etching mask used at the time of opening a trench opening portion has a multi-layer structure including a silicon nitride film and a polycrystal silicon film; the polycrystal silicon film is used as an etching stopper at the time of pre-planarization; and the silicon nitride film is used as an etching stopper at the time of polishing by a CMP method in order to remove simultaneously the excessive insulating film and the polycrystal silicon film to expose and a surface of the substrate, which is the active region, whereby the trench isolation having a satisfactory shape is obtainable.

摘要翻译： 一种制造半导体器件的方法，其具有通过HDP-CVD方法嵌入绝缘膜的具有微连接沟槽隔离的半导体器件，包括：通过相对于表面上层压的绝缘膜选择性地进行干蚀刻来进行预平面化的步骤 作为活性区域的基板，以及通过CMP方法进行研磨以提高绝缘膜的表面平坦性的步骤，其中在开口沟槽部分时使用的蚀刻掩模具有多层结构， 包括氮化硅膜和多晶硅膜的层结构; 多晶硅膜在预平面化时用作蚀刻阻挡层; 并且在通过CMP方法研磨时，氮化硅膜用作蚀刻阻挡层，以便同时去除过量绝缘膜和多晶硅膜以暴露作为活性区域的基板的表面，由此 可获得具有令人满意的形状的沟槽隔离。

公开(公告)号：US06218262B1

公开(公告)日：2001-04-17

申请号：US09200469

申请日：1998-11-27

申请人： Takashi Kuroi ,  Maiko Sakai ,  Katsuyuki Horita ,  Hirokazu Sayama

发明人： Takashi Kuroi ,  Maiko Sakai ,  Katsuyuki Horita ,  Hirokazu Sayama

IPC分类号： H01L21335

CPC分类号： H01L23/544 ,  H01L21/0274 ,  H01L21/32139 ,  H01L21/76229 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

摘要翻译： 本发明提供一种半导体器件，其包括沟槽型元件隔离，其在不劣化器件能力的情况下进行精确对准，以及制造这种半导体器件的方法。 由于在沟槽（10A）的边缘邻近区域中形成虚拟栅电极（14A），所以实现了不产生蚀刻余量的结构。 此外，由于在虚拟栅极电极（14A）的表面上设置高差，使得高度差反映了氧化硅膜（2A）的表面和硅表面之间的预备高度差 基板（1），可以使用伪栅电极本身（14A）作为对准标记。

公开(公告)号：US6127737A

公开(公告)日：2000-10-03

申请号：US943520

申请日：1997-10-03

申请人： Takashi Kuroi ,  Katsuyuki Horita ,  Maiko Sakai ,  Yasuo Inoue

发明人： Takashi Kuroi ,  Katsuyuki Horita ,  Maiko Sakai ,  Yasuo Inoue

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/544

CPC分类号： H01L21/76232 ,  H01L21/76229

摘要： In a semiconductor device with a trench-type element isolation structure, alignment can be performed with high accuracy without any deterioration in device performance. The surfaces of silicon oxide films (2B, 2C) embedded in trenches (10B, 10C) of an element forming region including a memory cell region (11B) and a peripheral circuit region (11C) in a semiconductor substrate (1), respectively, are almost level with the surface of the semiconductor substrate (1). On the other hand, the surface of a silicon oxide film (2A) embedded in a trench (10A) is formed lower than the surface of the semiconductor substrate (1).

摘要翻译： 在具有沟槽型元件隔离结构的半导体器件中，可以高精度地进行对准，而不会使器件性能下降。 分别在半导体衬底（1）中嵌入包括存储单元区域（11B）的元件形成区域和外围电路区域（11C）的沟槽（10B，10C）中的氧化硅膜（2B，2C）的表面， 几乎与半导体衬底（1）的表面一致。 另一方面，嵌入在沟槽（10A）中的氧化硅膜（2A）的表面形成为低于半导体衬底（1）的表面。

公开(公告)号：US6034409A

公开(公告)日：2000-03-07

申请号：US24312

申请日：1998-02-17

申请人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/10

CPC分类号： H01L21/76232

摘要： A semiconductor device comprising a semiconductor substrate, a trench formed in the substrate and having an inner wall including a sidewall and a bottom surface, a silicon oxide film deposited on the inner wall, and a buried oxide film deposited on the silicon oxide film to bury the trench, wherein the sidewall has portions of a sidewall sloped at a first profile angle A1, a second profile angle A2 and a third profile angle A3 from a surface of the substrate toward the bottom surface of the trench, and the profile angles have a relationship of A1

摘要翻译： 一种半导体器件，包括半导体衬底，形成在衬底中并具有包括侧壁和底表面的内壁的沟槽，沉积在内壁上的氧化硅膜和沉积在氧化硅膜上的掩埋氧化膜以埋入 沟槽，其中侧壁具有从基板的表面到沟槽的底表面以第一轮廓角A1倾斜的侧壁的第二轮廓角A2和第三轮廓角A3，并且轮廓角具有 A1