公开(公告)号：US5822268A

公开(公告)日：1998-10-13

申请号：US927158

申请日：1997-09-11

申请人： Toshiaki Kirihata

发明人： Toshiaki Kirihata

IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C7/10 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/1006 ,  G11C8/12

摘要： A multi-bank DRAM having a hierarchical column select line architecture is described. The DRAM is provided with a plurality of memory cells which are organized in at least two banks. Each of the banks includes memory cells which are arranged in rows and columns. The memory cells store data provided by at least one bit line and at least one data line. The DRAM includes: a first switch for selecting one of the two banks; and a second switch connected to the first switch for selecting one of the columns, wherein the first and second switches couple one of the bit lines to one of the data lines, enabling data to be written into or read out of memory cells common to the selected bank and to the selected column. The first switch is controlled by a plurality of bank CSLs (BCSLs), wherein the BCSLs are shared by some of the blocks within the same bank, but not by any of the blocks in other banks. The second switch is controlled by a plurality of global CSLs (GCSLs), the GCSLs being shared by all remaining banks within a unit. The BCSLs and GCSLs are controlled by the bank column decoder and by the global column decoder.

摘要翻译： 描述具有分层列选择线架构的多存储体DRAM。 DRAM具有被组织在至少两个组中的多个存储单元。 每个存储体包括排列成行和列的存储单元。 存储器单元存储由至少一个位线和至少一个数据线提供的数据。 DRAM包括：用于选择两个银行之一的第一开关; 以及第二开关，其连接到所述第一开关，用于选择所述列之一，其中所述第一和第二开关将所述位线中的一个耦合到所述数据线中的一个，使得能够将数据写入或读出与 选定的银行和选定的列。 第一开关由多个银行CSL（BCSL）控制，其中BCSL由同一银行内的一些块共享，但不由其他银行中的任何块共享。 第二开关由多个全局CSL（GCSL）控制，GCSL由单元内的所有剩余的单元共享。 BCSL和GCSL由银行列解码器和全局列解码器控制。

公开(公告)号：US5691946A

公开(公告)日：1997-11-25

申请号：US758783

申请日：1996-12-03

申请人： John DeBrosse ,  Toshiaki Kirihata ,  Hing Wong

发明人： John DeBrosse ,  Toshiaki Kirihata ,  Hing Wong

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C29/80 ,  G11C29/808 ,  G11C29/84

摘要： Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.

摘要翻译： 有效减少设计空间的行冗余控制电路与字方向平行排列，并配置在冗余块的底部。 通过引入（1）与本地行冗余线共享的分裂全局总线，（2）半长度单向行冗余字线使能信号线，可以有效地布置冗余控制块 这允许节省空间，以及（3）分布式字线使能解码器被设计为利用节省的空间。 由地址与时序偏差引起的非法正常/冗余访问问题也已解决。 通过使用其相邻的冗余匹配检测在本地给出该检测所需的定时。 这允许电路作为地址驱动电路完全操作，导致快速可靠的冗余匹配检测。 此外，通过使用行冗余匹配检测来生成采样字线使能信号（SWLE）。 一个双输入或门允许SWLE设置采样字线（SWL）的时间与字线使能（WLE）信号设置字线（WL）的时间相同。 无论模式如何，SWLE设置SWL的时间保持一致，从而消除了现有的可靠性问题。 该双输入OR门与行冗余匹配检测相结合，可作为理想的采样字线使能发生器。

公开(公告)号：US5544113A

公开(公告)日：1996-08-06

申请号：US346965

申请日：1994-11-30

申请人： Toshiaki Kirihata ,  Yohji Watanabe

发明人： Toshiaki Kirihata ,  Yohji Watanabe

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808

摘要： A wide Input/Output (I/O) Random Access Memory (RAM) with more efficient redundancy. The RAM array may be divided into individual units. Each unit is further divided into subarray blocks (blocks of subarrays). Each subarray or segment is organized by one and includes one spare column and may include spare word lines. When a block is accessed, only half of the segments are accessed. Whenever a segment is accessed, the segment's spare column is not. The spare columns from the unaccessed half block are available for repairing defective columns in the accessed half block. Data from columns in the accessed half and spare columns in the unaccessed half are transferred to Local Data Lines (LDLs) and from LDLs to Master Data Lines (MDLs). Valid data from accessed column lines and from selected spare lines are provided on the MDLS to second sense amplifiers. Defective columns are electrically replaced with spares after the second stage amplifiers. Thus, all of the spare columns in each half of each subarray block are available to replace an equal number of failed columns at any location in any segment in the other half block.

摘要翻译： 具有更高效冗余的宽输入/输出（I / O）随机存取存储器（RAM）。 RAM阵列可以被分成单独的单元。 每个单元进一步分为子阵列（子阵列）。 每个子阵列或段由一个组成，并且包括一个备用列，并且可以包括备用字线。 访问块时，仅访问一半的段。 无论何时访问段，段的备用列都不存在。 来自未加工的半块的备用列可用于修复访问的半块中的有缺陷的列。 未访问的一半中的列中的数据和未加工的一半中的备用列的数据将传输到本地数据线（LDL），并从LDL传输到主数据线（MDL）。 在MDLS上向第二读出放大器提供来自所访问列线和选定备用线路的有效数据。 在第二级放大器之后，有缺陷的列被替换为备件。 因此，每个子阵列块的每一半中的所有备用列可用于在另一半块中的任何段中的任何位置处替换相等数量的故障列。

公开(公告)号：US5483179A

公开(公告)日：1996-01-09

申请号：US230265

申请日：1994-04-20

申请人： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

发明人： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

IPC分类号： H03K17/687 ,  G05F3/24 ,  H03K19/0175 ,  H01L25/00

CPC分类号： G05F3/24

摘要： A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.

摘要翻译： 用于控制跨越NMOS上拉晶体管的电压的装置，其包括可能暴露于可变电压的源节点。 该器件还包括可以暴露于可变电压的栅极节点。 控制部分调节施加到栅极节点的电压，其中源节点和栅极节点之间的电压差被限制到期望的电平。

公开(公告)号：US08590010B2

公开(公告)日：2013-11-19

申请号：US13302314

申请日：2011-11-22

申请人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

发明人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

IPC分类号： H03M13/05

CPC分类号： G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

摘要翻译： 随机内在芯片ID生成采用保留失败签名。 使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。 保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。 验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。 认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。 中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。 在每次ID读取操作中改变中间条件，导致更安全的识别。

公开(公告)号：US20130168673A1

公开(公告)日：2013-07-04

申请号：US13342226

申请日：2012-01-03

申请人： Xiaojun Yu ,  Anda C. Mocuta ,  Toshiaki Kirihata

发明人： Xiaojun Yu ,  Anda C. Mocuta ,  Toshiaki Kirihata

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L23/481 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.

摘要翻译： 一种设备，包括通过硅通孔（TSV）连接IDVMON监视器，以使监视器能够连接到位于晶片背面的探针焊盘。 因为晶片的背面具有比前侧大得多的空间，所以可以容纳用于IDVMON的探针垫，而不牺牲硅面积。

公开(公告)号：US20130133031A1

公开(公告)日：2013-05-23

申请号：US13302314

申请日：2011-11-22

申请人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

发明人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

IPC分类号： G06F21/00

CPC分类号： G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

摘要翻译： 随机内在芯片ID生成采用保留失败签名。 使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。 保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。 验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。 认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。 中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。 在每次ID读取操作中改变中间条件，导致更安全的识别。

公开(公告)号：US07764531B2

公开(公告)日：2010-07-27

申请号：US12212738

申请日：2008-09-18

申请人： Anthony Gus Aipperspach ,  Toshiaki Kirihata ,  Phil Christopher Felice Paone ,  Brian Joy Reed ,  John Matthew Safran ,  David Edward Schmitt ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  Toshiaki Kirihata ,  Phil Christopher Felice Paone ,  Brian Joy Reed ,  John Matthew Safran ,  David Edward Schmitt ,  Gregory John Uhlmann

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse.

摘要翻译： 一种用于实现精确的eFuse电阻测量的方法和电路，以及设置有该电路所在的设计结构。 耦合到eFuse阵列并用于电流测量的eFuse读出放大器包括平衡奇数和偶数位线以及连接到平衡奇数位和偶数位线的多个可编程参考电阻。 首先，通过一个可编程参考电阻进行基线电流测量，并用于识别网络基线电阻。 对包括所选择的eFuse的eFuse路径进行电流测量，并用于识别所选eFuse的电阻。

公开(公告)号：US20090212850A1

公开(公告)日：2009-08-27

申请号：US12037176

申请日：2008-02-26

申请人： Anthony Gus Aipperspach ,  Toshiaki Kirihata ,  Phil Christopher Felice Paone ,  Brian Joy Reed ,  David Edward Schmitt ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  Toshiaki Kirihata ,  Phil Christopher Felice Paone ,  Brian Joy Reed ,  David Edward Schmitt ,  Gregory John Uhlmann

IPC分类号： H01H37/76

CPC分类号： G11C29/02 ,  G11C17/18 ,  G11C29/027

摘要： A method and circuit for implementing eFuse resistance screening, and a design structure on which the subject circuit resides are provided. An eFuse is sensed using a first reference resistor. Responsive to the eFuse being sensed as blown with the first reference resistor, the eFuse is sensed using a second reference resistor having a higher resistance than the first reference resistor. Responsive to the eFuse being sensed as unblown with the second reference resistor, the eFuse is recorded as poorly blown. Reliability concerns are identified quickly and accurately without being required to measure the resistance of the eFuse.

摘要翻译： 一种用于实现eFuse电阻屏蔽的方法和电路，以及设置有该电路所在的设计结构。 使用第一参考电阻感测eFuse。 响应于被感测为与第一参考电阻一起被吹扫的eFuse，使用具有比第一参考电阻器更高的电阻的第二参考电阻来感测eFuse。 eFuse响应于被第二参考电阻感应为未被吹扫，eFuse被记录为不良。 快速准确地识别可靠性问题，而不需要测量eFuse的电阻。

公开(公告)号：US20050157577A1

公开(公告)日：2005-07-21

申请号：US10757846

申请日：2004-01-15

申请人： John Barth ,  Toshiaki Kirihata ,  Paul Parries

发明人： John Barth ,  Toshiaki Kirihata ,  Paul Parries

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

摘要： A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.