利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

59 条记录 (耗时 0.032 秒)

    APPARATUS AND METHOD FOR COLLECTING SHOPPING INFORMATION USING MAGNETIC SENSOR
    41.
    发明申请
    APPARATUS AND METHOD FOR COLLECTING SHOPPING INFORMATION USING MAGNETIC SENSOR 审中-公开
    使用磁传感器收集购物信息的装置和方法

    公开(公告)号：US20100089993A1

    公开(公告)日：2010-04-15

    申请号：US12517543

    申请日：2007-10-24

    申请人： Chang-Sub Shin ,  In-Hwan Lee ,  Bong-Soo Kim ,  Cheol-Sig Pyo

    发明人： Chang-Sub Shin ,  In-Hwan Lee ,  Bong-Soo Kim ,  Cheol-Sig Pyo

    IPC分类号： G06Q99/00

    CPC分类号： G06Q30/06 ,  G06Q30/02

    摘要： Provided are an apparatus and method for collecting shopping information using a magnetic sensor. The shopping information collecting apparatus, includes: a magnetic value sensing and analyzing means for sensing and analyzing a magnetic value within own zone in real-time; a central processing means for processing shopping information based on the magnetic value analyzed by the magnetic value sensing and analyzing means; and a shopping information transmitting means for transmitting shopping information processed by the central processing means.

    摘要翻译： 提供了一种使用磁传感器收集购物信息的装置和方法。 购物信息收集装置包括：实时检测和分析本区域内的磁值的磁值检测和分析装置; 用于基于由磁值检测和分析装置分析的磁值来处理购物信息的中央处理装置; 以及购买信息发送装置，用于发送由中央处理装置处理的购物信息。

    Apparatuses and methods for automatic wavelength locking of an optical transmitter to the wavelength of an injected incoherent light signal
    42.
    发明授权
    Apparatuses and methods for automatic wavelength locking of an optical transmitter to the wavelength of an injected incoherent light signal 失效
    将光发射机自动波长锁定到注入的非相干光信号的波长的装置和方法

    公开(公告)号：US07593647B2

    公开(公告)日：2009-09-22

    申请号：US10528445

    申请日：2003-04-22

    申请人： Chang-Hee Lee ,  Kwang-Uk Chu ,  Bong-Soo Kim

    发明人： Chang-Hee Lee ,  Kwang-Uk Chu ,  Bong-Soo Kim

    IPC分类号： H04B10/04

    CPC分类号： H04B10/572

    摘要： An optical transmitter has a resonance wavelength characteristic that varies with the refractive index of the optical transmitter. The optical transmitter receives a narrow band injected wavelength signal from an incoherent light source. The controller substantially matches a resonant wavelength of the optical transmitter to the wavelength of the injected wavelength signal by changing the refractive index of the optical transmitter to substantially match the resonant wavelength of the optical transmitter and the wavelength of the injected wavelength signal. A detector measures a parameter of the optical transmitter to provide a feedback signal to a controller to determine when the resonant wavelength of the optical transmitter and the wavelength of the injected wavelength signal are substantially matched.

    摘要翻译： 光发射机具有随着光发射机的折射率而变化的谐振波长特性。 光发射机从非相干光源接收窄带注入的波长信号。 控制器通过改变光发射器的折射率与光发射机的谐振波长和注入的波长信号的波长基本匹配，使光发射机的谐振波长与注入的波长信号的波长匹配。 检测器测量光发射机的参数以向控制器提供反馈信号以确定光发射机的谐振波长和注入的波长信号的波长何时基本匹配。

    Semiconductor device having vertical transistor and method of fabricating the same
    43.
    发明申请
    Semiconductor device having vertical transistor and method of fabricating the same 有权
    具有垂直晶体管的半导体器件及其制造方法

    公开(公告)号：US20070080385A1

    公开(公告)日：2007-04-12

    申请号：US11450936

    申请日：2006-06-09

    申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

    发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

    摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

    摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

    Catalyst for removing aromatic halogenated compounds comprising dioxin, carbon monoxide, and nitrogen oxide and use thereof
    44.
    发明申请
    Catalyst for removing aromatic halogenated compounds comprising dioxin, carbon monoxide, and nitrogen oxide and use thereof 审中-公开
    用于除去包含二恶英，一氧化碳和氮氧化物的芳族卤代化合物的催化剂及其用途

    公开(公告)号：US20060258528A1

    公开(公告)日：2006-11-16

    申请号：US11491139

    申请日：2006-07-24

    申请人： Du-Soung Kim ,  Jihn-Koo Lee ,  Bong-Soo Kim ,  Seung-Jae Lee ,  Myoung-Jin Kha

    发明人： Du-Soung Kim ,  Jihn-Koo Lee ,  Bong-Soo Kim ,  Seung-Jae Lee ,  Myoung-Jin Kha

    IPC分类号： B01J23/00

    CPC分类号： B01J21/063 ,  B01D53/865 ,  B01D53/8662 ,  B01D2257/2064 ,  B01J23/18 ,  B01J23/682 ,  B01J23/683 ,  B01J23/686 ,  B01J23/687 ,  B01J27/053 ,  B01J35/04 ,  B01J37/0242

    摘要： The present invention relates to a catalyst for removing aromatic halogenated compounds comprising dioxin, carbon monoxide and nitrogen oxide simultaneously and a method for preparing the catalyst, more particularly, a catalyst comprising 0.1 to 5% by weight of vanadium, 1 to 12% by weight of metals in 6A family and 0.1 to 10% by weight of Ag in titania carrier or, alternatively, a catalyst produced by impregnating said catalyst in 0.05 to 1M sulfuric acid solution to carry out acid treatment. The catalyst according to the present invention has improved efficiency for removing 1,2-dichlorobenzene as a reactant model of dioxin and carbon monoxide rather than existing catalysts and also, alternative efficiency for removing nitrogen oxide substantially equal to commonly known catalysts, so that the catalyst can effectively control various air pollutants contained in exhaust gas.

    摘要翻译： 本发明涉及一种用于同时除去包含二恶英，一氧化碳和氮氧化物的芳族卤代化合物的催化剂，以及一种制备该催化剂的方法，更具体地说，涉及一种催化剂，其包含0.1-5重量％的钒，1至12重量％ 的6A族金属和0.1〜10重量％的Ag在二氧化钛载体中，或者是通过将所述催化剂浸渍在0.05〜1M硫酸溶液中进行酸处理而制备的催化剂。 根据本发明的催化剂具有提高的作为二恶英和一氧化碳的反应物模型的1,2-二氯苯的效率，而不是现有的催化剂，以及用于除去基本上等于通常已知的催化剂的氮氧化物的替代效率，使得催化剂 可有效控制废气中含有的各种空气污染物。

    Integrated circuit devices having buried interconnect structures therein that increase interconnect density
    46.
    发明授权
    Integrated circuit devices having buried interconnect structures therein that increase interconnect density 有权
    其中具有掩埋互连结构的集成电路器件增加互连密度

    公开(公告)号：US08729658B2

    公开(公告)日：2014-05-20

    申请号：US13789028

    申请日：2013-03-07

    申请人： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

    发明人： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

    IPC分类号： H01L29/00

    CPC分类号： H01L23/481 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.

    摘要翻译： 集成电路器件包括在其中具有多个沟槽隔离区域的半导体衬底，其中限定了它们之间的相应的半导体有源区。 沟槽设置在半导体衬底中。 沟槽具有分别限定与第一沟槽隔离区域和第一有源区域相对的界面的第一和第二相对的侧壁。 第一电互连设置在沟槽的底部。 提供了一种电绝缘覆盖图案，其在第一电互连和沟槽的顶部之间延伸。 还提供了互连绝缘层，其将沟槽的第一和第二侧壁和底部排列。 互连绝缘层在第一电互连和第一有源区之间延伸。 在第一活动区域设置有凹部。 凹部具有限定与互连绝缘层的界面的侧壁。 还提供了第二电互连，其延伸在：（i）第一沟槽隔离区的上表面，（ii）电绝缘封盖图案; 和（iii）凹槽的侧壁。 第一和第二电互连分别在第一和第二正交方向跨越半导体衬底延伸。

    Methods of Fabricating Semiconductor Devices Having Buried Word Line Interconnects
    48.
    发明申请
    Methods of Fabricating Semiconductor Devices Having Buried Word Line Interconnects 有权
    制造埋入字线互连的半导体器件的方法

    公开(公告)号：US20120264280A1

    公开(公告)日：2012-10-18

    申请号：US13473751

    申请日：2012-05-17

    申请人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

    发明人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

    IPC分类号： H01L21/768

    CPC分类号： H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

    摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

    摘要翻译： 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。

    Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode
    49.
    发明授权
    Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode 有权
    制造具有电池外延层的半导体器件的方法部分地覆盖埋电池栅电极

    公开(公告)号：US08053307B2

    公开(公告)日：2011-11-08

    申请号：US12662393

    申请日：2010-04-14

    申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

    发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

    摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

    摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。